[PATCH 1/6] arm64: dts: socfpga: agilex5: add DDR50 read-path tuning to sdmmc
From: tze . yee . ng
Date: Wed Sep 23 2026 - 04:27:02 EST
From: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>
Add the Cadence SD6HC DDR50 read-path tuning properties to the shared
Agilex5 sdmmc node so that boards enabling SD UHS DDR50 pick up sane
defaults for the loopback DQS selection and the read DQS delay:
- cdns,ddr50-use-lpbk-dqs = <0>
- cdns,ddr50-read-dqs-delay = <96>
Signed-off-by: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>
---
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 5f22e6d7ab85..dc25b7382a29 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -322,6 +322,8 @@ sdmmc: mmc@10808000 {
resets = <&rst SDMMC_RESET>, <&rst COMBOPHY_RESET>,
<&rst SDMMC_OCP_RESET>;
reset-names = "sdhc-reset", "combophy", "sdmmc-ocp";
+ cdns,ddr50-use-lpbk-dqs = <0>;
+ cdns,ddr50-read-dqs-delay = <96>;
status = "disabled";
};
--
2.43.7