[PATCH v1 4/4] ASoC: codecs: pm4125: Add the MBHC callbacks needed for jack detection
From: Mohammad Rafi Shaik
Date: Thu Oct 15 2026 - 10:16:53 EST
The codec only hands the MBHC framework the electrical bias and button
threshold callbacks, and leaves the rest of struct wcd_mbhc_cb empty.
The framework falls back to driving the shared register fields itself
for some of them, but it has no fallback at all for the ones that
control hardware it cannot describe generically, so plug type detection
runs without the RCO clock, without a micbias ramp and without the
headset ground detection comparator, and never gets a usable ADC
reading.
Add the callbacks the ADC based detection logic needs:
- clk_setup() enables the MBHC RCO, which clocks the detection FSM.
- micbias_enable_status() lets the framework tell whether MIC_BIAS_2
is already up for recording, so it does not switch the button
current source on underneath a capture stream.
- hph_pull_up_control() selects the HPHL pull up current used while
sensing an insertion, defaulting to 3uA as the hardware expects.
- mbhc_micbias_control() routes the framework's MIC_BIAS_2 requests
through pm4125_micbias_control() so they share the reference count
with the DAPM micbias widgets and with the analog master bias.
- mbhc_micb_ramp_control() ramps MIC_BIAS_2 instead of stepping it,
which is required before the cross connection check reads the
Schmitt trigger outputs.
- mbhc_micb_ctrl_thr_mic() raises MIC_BIAS_2 to the threshold needed
to tell a special headset from an extension cable, and puts it back
afterwards.
- get_micbias_val() reports the programmed MIC_BIAS_2 voltage. The
generic path assumes a 1V base, while this codec starts at 1.6V in
50mV steps, so the framework would scale every threshold wrongly.
- mbhc_gnd_det_ctrl() enables the headset ground pull up comparator
together with ground detection, in that order on the way up and the
reverse on the way down.
- hph_pull_down_ctrl() parks the headphone outputs in a pull down
while no jack is being driven.
pm4125_mbhc_micb_adjust_voltage() changes MIC_BIAS_2 while it is
enabled, which has to be done with the output briefly pulled up, so
serialise it against concurrent requests with a mutex.
Assisted-by: Claude Opus 5
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@xxxxxxxxxxxxxxxx>
---
sound/soc/codecs/pm4125.c | 188 ++++++++++++++++++++++++++++++++++++++++++++++
sound/soc/codecs/pm4125.h | 13 ++++
2 files changed, 201 insertions(+)
diff --git a/sound/soc/codecs/pm4125.c b/sound/soc/codecs/pm4125.c
index 2100f4e36..6dd5ce0f4 100644
--- a/sound/soc/codecs/pm4125.c
+++ b/sound/soc/codecs/pm4125.c
@@ -8,6 +8,7 @@
#include <linux/irqdomain.h>
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
@@ -76,6 +77,8 @@ struct pm4125_priv {
struct regmap_irq_chip_data *irq_chip;
struct snd_soc_jack *jack;
unsigned long status_mask;
+ /* Protects micbias voltage adjustment against concurrent requests */
+ struct mutex micb_lock;
s32 micb_ref[PM4125_MAX_MICBIAS];
s32 pullup_ref[PM4125_MAX_MICBIAS];
@@ -968,6 +971,12 @@ static int pm4125_set_swr_port(struct snd_kcontrol *kcontrol, struct snd_ctl_ele
return 1;
}
+static void pm4125_mbhc_clk_setup(struct snd_soc_component *component, bool enable)
+{
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_CTL_1,
+ PM4125_ANA_MBHC_CTL_RCO_EN_MASK, enable);
+}
+
static void pm4125_mbhc_bias_control(struct snd_soc_component *component, bool enable)
{
snd_soc_component_write_field(component, PM4125_ANA_MBHC_ELECT,
@@ -995,9 +1004,187 @@ static void pm4125_mbhc_program_btn_thr(struct snd_soc_component *component,
}
}
+static bool pm4125_mbhc_micb_en_status(struct snd_soc_component *component, int micb_num)
+{
+ if (micb_num != MIC_BIAS_2)
+ return false;
+
+ return snd_soc_component_read_field(component, PM4125_ANA_MICBIAS_MICB_1_2_EN,
+ PM4125_ANA_MICBIAS_MICB2_EN_MASK) == 1;
+}
+
+static void pm4125_mbhc_hph_l_pull_up_control(struct snd_soc_component *component,
+ enum mbhc_hs_pullup_iref pull_up_cur)
+{
+ /* Default pull up current to 3uA */
+ if (pull_up_cur < I_OFF || pull_up_cur > I_3P0_UA || pull_up_cur == I_DEFAULT)
+ pull_up_cur = I_3P0_UA;
+
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_PLUG_DETECT_CTL,
+ PM4125_ANA_MBHC_HSDET_PULLUP_C_MASK, pull_up_cur);
+}
+
+static int pm4125_mbhc_request_micbias(struct snd_soc_component *component,
+ int micb_num, int req)
+{
+ return pm4125_micbias_control(component, micb_num, req, false);
+}
+
+static void pm4125_mbhc_micb_ramp_control(struct snd_soc_component *component, bool enable)
+{
+ if (enable) {
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MICB2_RAMP,
+ PM4125_ANA_MBHC_MICB2_RAMP_SHIFT_MASK,
+ PM4125_ANA_MBHC_MICB2_RAMP_SHIFT_CTRL);
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MICB2_RAMP,
+ PM4125_ANA_MBHC_MICB2_RAMP_EN_MASK, 1);
+ } else {
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MICB2_RAMP,
+ PM4125_ANA_MBHC_MICB2_RAMP_EN_MASK, 0);
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MICB2_RAMP,
+ PM4125_ANA_MBHC_MICB2_RAMP_SHIFT_MASK, 0);
+ }
+}
+
+static int pm4125_mbhc_micb_adjust_voltage(struct snd_soc_component *component,
+ int req_volt, int micb_num)
+{
+ struct pm4125_priv *pm4125 = snd_soc_component_get_drvdata(component);
+ int cur_vout_ctl, req_vout_ctl, micb_en, ret = 0;
+ unsigned int pullup_mask, en_mask;
+
+ switch (micb_num) {
+ case MIC_BIAS_1:
+ pullup_mask = PM4125_ANA_MICBIAS_MICB1_PULL_UP_MASK;
+ en_mask = PM4125_ANA_MICBIAS_MICB1_EN_MASK;
+ break;
+ case MIC_BIAS_2:
+ pullup_mask = PM4125_ANA_MICBIAS_MICB2_PULL_UP_MASK;
+ en_mask = PM4125_ANA_MICBIAS_MICB2_EN_MASK;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ mutex_lock(&pm4125->micb_lock);
+
+ /*
+ * If requested micbias voltage is same as current micbias voltage,
+ * then just return. Otherwise, adjust voltage as per requested value.
+ * If micbias is already enabled, then to avoid slow micbias ramp-up
+ * or down enable pull-up momentarily, change the micbias value and
+ * then re-enable micbias.
+ */
+ micb_en = snd_soc_component_read_field(component, PM4125_ANA_MICBIAS_MICB_1_2_EN,
+ en_mask);
+ cur_vout_ctl = snd_soc_component_read_field(component, PM4125_ANA_MICBIAS_LDO_1_SETTING,
+ PM4125_ANA_MICBIAS_MICB_OUT_VAL_MASK);
+
+ req_vout_ctl = pm4125_get_micb_vout_ctl_val(component->dev, req_volt);
+ if (req_vout_ctl < 0) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ if (cur_vout_ctl == req_vout_ctl)
+ goto exit;
+
+ if (micb_en == 1)
+ snd_soc_component_write_field(component, PM4125_ANA_MICBIAS_MICB_1_2_EN,
+ pullup_mask,
+ PM4125_ANA_MICBIAS_MICB_PULL_ENABLE);
+
+ snd_soc_component_write_field(component, PM4125_ANA_MICBIAS_LDO_1_SETTING,
+ PM4125_ANA_MICBIAS_MICB_OUT_VAL_MASK, req_vout_ctl);
+
+ if (micb_en == 1) {
+ snd_soc_component_write_field(component, PM4125_ANA_MICBIAS_MICB_1_2_EN,
+ pullup_mask,
+ PM4125_ANA_MICBIAS_MICB_PULL_DISABLE);
+ /* Add 2ms delay as per HW requirement after enabling micbias */
+ usleep_range(2000, 2100);
+ }
+exit:
+ mutex_unlock(&pm4125->micb_lock);
+
+ return ret;
+}
+
+static int pm4125_mbhc_micb_ctrl_threshold_mic(struct snd_soc_component *component,
+ int micb_num, bool req_en)
+{
+ struct pm4125_priv *pm4125 = snd_soc_component_get_drvdata(component);
+ int micb_mv;
+
+ if (micb_num != MIC_BIAS_2)
+ return -EINVAL;
+
+ /*
+ * If device tree micbias level is already above the minimum voltage
+ * needed to detect threshold microphone, then do not change the
+ * micbias, just return.
+ */
+ if (pm4125->micb2_mv >= WCD_MBHC_THR_HS_MICB_MV)
+ return 0;
+
+ micb_mv = req_en ? WCD_MBHC_THR_HS_MICB_MV : pm4125->micb2_mv;
+
+ return pm4125_mbhc_micb_adjust_voltage(component, micb_mv, MIC_BIAS_2);
+}
+
+static void pm4125_mbhc_get_micbias_val(struct snd_soc_component *component, int *mb)
+{
+ u8 vout_ctl;
+
+ /* Read MBHC Micbias (Mic Bias2) voltage */
+ vout_ctl = snd_soc_component_read_field(component, PM4125_ANA_MICBIAS_LDO_1_SETTING,
+ PM4125_ANA_MICBIAS_MICB_OUT_VAL_MASK);
+
+ /*
+ * Formula for getting micbias from vout:
+ * micbias = 1.6V + VOUT_CTL * 50mV
+ */
+ *mb = 1600 + (vout_ctl * 50);
+}
+
+static void pm4125_mbhc_gnd_det_ctrl(struct snd_soc_component *component, bool enable)
+{
+ if (enable) {
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MECH,
+ PM4125_ANA_MBHC_HSG_PULLUP_COMP_EN_MASK, 1);
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MECH,
+ PM4125_ANA_MBHC_GND_DET_EN_MASK, 1);
+ } else {
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MECH,
+ PM4125_ANA_MBHC_GND_DET_EN_MASK, 0);
+ snd_soc_component_write_field(component, PM4125_ANA_MBHC_MECH,
+ PM4125_ANA_MBHC_HSG_PULLUP_COMP_EN_MASK, 0);
+ }
+}
+
+static void pm4125_mbhc_hph_pull_down_ctrl(struct snd_soc_component *component, bool enable)
+{
+ u8 val = enable ? PM4125_ANA_HPHPA_CNP_GND_PULL_DOWN :
+ PM4125_ANA_HPHPA_CNP_GND_PULL_NONE;
+
+ snd_soc_component_write_field(component, PM4125_ANA_HPHPA_CNP_CTL_2,
+ PM4125_ANA_HPHPA_CNP_GND_L_MASK, val);
+ snd_soc_component_write_field(component, PM4125_ANA_HPHPA_CNP_CTL_2,
+ PM4125_ANA_HPHPA_CNP_GND_R_MASK, val);
+}
+
static const struct wcd_mbhc_cb mbhc_cb = {
+ .clk_setup = pm4125_mbhc_clk_setup,
.mbhc_bias = pm4125_mbhc_bias_control,
.set_btn_thr = pm4125_mbhc_program_btn_thr,
+ .micbias_enable_status = pm4125_mbhc_micb_en_status,
+ .hph_pull_up_control = pm4125_mbhc_hph_l_pull_up_control,
+ .mbhc_micbias_control = pm4125_mbhc_request_micbias,
+ .mbhc_micb_ramp_control = pm4125_mbhc_micb_ramp_control,
+ .mbhc_micb_ctrl_thr_mic = pm4125_mbhc_micb_ctrl_threshold_mic,
+ .get_micbias_val = pm4125_mbhc_get_micbias_val,
+ .mbhc_gnd_det_ctrl = pm4125_mbhc_gnd_det_ctrl,
+ .hph_pull_down_ctrl = pm4125_mbhc_hph_pull_down_ctrl,
};
static int pm4125_mbhc_init(struct snd_soc_component *component)
@@ -1692,6 +1879,7 @@ static int pm4125_probe(struct platform_device *pdev)
return dev_err_probe(dev, ret, "Failed to get micbias\n");
atomic_set(&pm4125->gloal_mbias_cnt, 0);
+ mutex_init(&pm4125->micb_lock);
cfg = &pm4125->mbhc_cfg;
cfg->mbhc_micbias = MIC_BIAS_2;
diff --git a/sound/soc/codecs/pm4125.h b/sound/soc/codecs/pm4125.h
index 25fd3106f..3ee6f9c25 100644
--- a/sound/soc/codecs/pm4125.h
+++ b/sound/soc/codecs/pm4125.h
@@ -13,7 +13,9 @@
#define PM4125_DIG_BASE_ADDR 0x3400
#define PM4125_ANA_MICBIAS_MICB_1_2_EN (PM4125_ANA_BASE_ADDR+0x040)
+#define PM4125_ANA_MICBIAS_MICB1_EN_MASK BIT(6)
#define PM4125_ANA_MICBIAS_MICB1_PULL_UP_MASK BIT(5)
+#define PM4125_ANA_MICBIAS_MICB2_EN_MASK BIT(2)
#define PM4125_ANA_MICBIAS_MICB2_PULL_UP_MASK BIT(1)
#define PM4125_ANA_MICBIAS_MICB2_PULL_DN_MASK BIT(0)
#define PM4125_ANA_MICBIAS_MICB_PULL_ENABLE 1
@@ -25,6 +27,8 @@
#define PM4125_ANA_TX_AMIC1 (PM4125_ANA_BASE_ADDR+0x047)
#define PM4125_ANA_TX_AMIC2 (PM4125_ANA_BASE_ADDR+0x048)
#define PM4125_ANA_MBHC_MECH (PM4125_ANA_BASE_ADDR+0x05A)
+#define PM4125_ANA_MBHC_GND_DET_EN_MASK BIT(6)
+#define PM4125_ANA_MBHC_HSG_PULLUP_COMP_EN_MASK BIT(1)
#define PM4125_ANA_MBHC_ELECT (PM4125_ANA_BASE_ADDR+0x05B)
#define PM4125_ANA_MBHC_ELECT_BIAS_EN_MASK BIT(0)
#define PM4125_ANA_MBHC_ELECT_BIAS_ENABLE 1
@@ -40,9 +44,14 @@
#define PM4125_ANA_MBHC_BTN3_ZDET_DBG_400 (PM4125_ANA_BASE_ADDR+0x063)
#define PM4125_ANA_MBHC_BTN4_ZDET_DBG_1400 (PM4125_ANA_BASE_ADDR+0x064)
#define PM4125_ANA_MBHC_MICB2_RAMP (PM4125_ANA_BASE_ADDR+0x065)
+#define PM4125_ANA_MBHC_MICB2_RAMP_EN_MASK BIT(7)
+#define PM4125_ANA_MBHC_MICB2_RAMP_SHIFT_MASK GENMASK(4, 2)
+#define PM4125_ANA_MBHC_MICB2_RAMP_SHIFT_CTRL 3
#define PM4125_ANA_MBHC_CTL_1 (PM4125_ANA_BASE_ADDR+0x066)
+#define PM4125_ANA_MBHC_CTL_RCO_EN_MASK BIT(7)
#define PM4125_ANA_MBHC_CTL_2 (PM4125_ANA_BASE_ADDR+0x067)
#define PM4125_ANA_MBHC_PLUG_DETECT_CTL (PM4125_ANA_BASE_ADDR+0x068)
+#define PM4125_ANA_MBHC_HSDET_PULLUP_C_MASK GENMASK(7, 6)
#define PM4125_ANA_MBHC_ZDET_ANA_CTL (PM4125_ANA_BASE_ADDR+0x069)
#define PM4125_ANA_MBHC_ZDET_RAMP_CTL (PM4125_ANA_BASE_ADDR+0x06A)
#define PM4125_ANA_MBHC_FSM_STATUS (PM4125_ANA_BASE_ADDR+0x06B)
@@ -58,6 +67,10 @@
#define PM4125_ANA_HPHPA_CNP_CTL_1_EN_MASK BIT(1)
#define PM4125_ANA_HPHPA_CNP_CTL_1_EN 1
#define PM4125_ANA_HPHPA_CNP_CTL_2 (PM4125_ANA_BASE_ADDR+0x084)
+#define PM4125_ANA_HPHPA_CNP_GND_L_MASK GENMASK(5, 4)
+#define PM4125_ANA_HPHPA_CNP_GND_R_MASK GENMASK(3, 2)
+#define PM4125_ANA_HPHPA_CNP_GND_PULL_DOWN 2
+#define PM4125_ANA_HPHPA_CNP_GND_PULL_NONE 0
#define PM4125_ANA_HPHPA_CNP_OCP_EN_L_MASK BIT(1)
#define PM4125_ANA_HPHPA_CNP_OCP_EN_R_MASK BIT(0)
#define PM4125_ANA_HPHPA_CNP_OCP_ENABLE 1
--
2.34.1