[PATCH DNM RFC 13/16] arm64: dts: qcom: sm8650: Describe clock controller power rails

[Konrad Dybcio]

From: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>

The SM8650 clock-controller nodes omit rails needed by their clocks and
PLLs. Without those connections, the clock-owned DVFS implementation
cannot attach its voters to all required domains and controller probe
can fail before any clocks are registered.

Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
Assisted-by: LLM
Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/sm8650.dtsi | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 86fbb0fd6472..0847cfb35954 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -2017,8 +2017,9 @@ gcc: clock-controller@100000 {
 				 <&ufs_mem_phy 1>,
 				 <&ufs_mem_phy 2>,
 				 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
-
-			power-domains = <&rpmhpd RPMHPD_CX>;
+			power-domains = <&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_CX_AO>,
+					<&rpmhpd RPMHPD_MX>;
 
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -4364,6 +4365,10 @@ gpucc: clock-controller@3d90000 {
 			clocks = <&bi_tcxo_div2>,
 				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
 				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+			power-domains = <&rpmhpd RPMHPD_MX>,
+					<&rpmhpd RPMHPD_CX>,
+					<&rpmhpd RPMHPD_MXC>,
+					<&rpmhpd RPMHPD_GFX>;
 
 			#clock-cells = <1>;
 			#reset-cells = <1>;
@@ -5639,7 +5644,8 @@ camcc: clock-controller@ade0000 {
 				 <&bi_tcxo_ao_div2>,
 				 <&sleep_clk>;
 			power-domains = <&rpmhpd RPMHPD_MMCX>,
-					<&rpmhpd RPMHPD_MXC>;
+					<&rpmhpd RPMHPD_MXC>,
+					<&rpmhpd RPMHPD_MX>;
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;
@@ -6049,8 +6055,8 @@ dispcc: clock-controller@af00000 {
 				 <0>, /* dp3 */
 				 <0>;
 
-			power-domains = <&rpmhpd RPMHPD_MMCX>;
-			required-opps = <&rpmhpd_opp_low_svs>;
+			power-domains = <&rpmhpd RPMHPD_MMCX>,
+					<&rpmhpd RPMHPD_MX>;
 
 			#clock-cells = <1>;
 			#reset-cells = <1>;

-- 
2.56.0