RE: [PATCH v2 0/3] clk: renesas: rzg2l: Unify SAM PLL configuration macros

[Biju Das]

Hi all,

I noticed that there is a patch conflict with renesas-clk/next for patch#2.
I will rebase and send v3. Sorry for the inconvenience.

Cheers,
Biju

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 18 May 2026 10:40
> Subject: [PATCH v2 0/3] clk: renesas: rzg2l: Unify SAM PLL configuration macros
> 
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> 
> This series cleans up and unifies the SAM PLL configuration macros across the RZ/G2L, RZ/G3S, RZ/G3L,
> and RZ/V2M CPG drivers.
> 
> Currently, each SoC family defines its own local macro for encoding PLL register offsets into a conf
> field (PLL146_CONF, G3S_PLL146_CONF, G3L_PLL1467_CONF, PLL4_CONF), and the driver uses separate decode
> macros (GET_REG_SAMPLL_CLK1, GET_REG_SAMPLL_CLK2, GET_REG_SAMPLL_SETTING) to retrieve register offsets
> at runtime. This leads to duplicated logic and implicit coupling between PLL index and register layout.
> 
> The series introduces a pair of shared macros, CPG_SAM_PLL_CONF(stby) and CPG_PLL_CONF(stby, setting),
> that encode only the standby offset and optional setting field. CLK1/CLK2 register offsets are then
> derived from the standby offset using fixed +0x4/+0x8 deltas via new CPG_PLL_*_OFFSET() helpers,
> removing the need for separate CLK1/CLK2 fields in the conf value.
> 
> Finally, the RZG3L-prefixed STBY/MON macros are renamed to CPG-prefixed equivalents to reflect their
> shared nature across SoC families.
> 
> v1->v2:
>  * Dropped the dependency from the cover letter as the patch hits next.
>  * Collected the tag
>  * Updated commit description for patch#2.
>  * Fixed the macro RZG3L_PLL_STBY_OFFSET by using CPG_PLL_STBY_OFFSET.
>  * Moved CPG_PLL_STBY_{RESETB_WEN,RESETB} near to CPG_PLL_STBY_OFFSET.
>  * Reorderd the above macros
>  * Moved CPG_PLL_MON_{LOCK,RESETB} near to CPG_PLL_MON_OFFSET.
>  * Reorderd the above macros
>  * Dropped a blank line.
> 
> Biju Das (3):
>   clk: renesas: rzg2l: Simplify SAM PLL configuration macro
>   clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro
>   clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed
>     ones
> 
>  drivers/clk/renesas/r9a07g043-cpg.c |  2 +-  drivers/clk/renesas/r9a07g044-cpg.c |  2 +-
> drivers/clk/renesas/r9a08g045-cpg.c |  5 +---  drivers/clk/renesas/r9a08g046-cpg.c |  7 ++---
> drivers/clk/renesas/r9a09g011-cpg.c |  7 +----
>  drivers/clk/renesas/rzg2l-cpg.c     | 40 ++++++++++++++---------------
>  drivers/clk/renesas/rzg2l-cpg.h     |  7 ++---
>  7 files changed, 28 insertions(+), 42 deletions(-)
> 
> --
> 2.43.0