[PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider

[Demeter Barna via B4 Relay]

From: Demeter Barna <me@xxxxxxxxxxxxxxxxxxx>

Add the EPSS L3 block, already documented as qcom,sm8350-epss-l3, so
that the CPUs can vote for the L3 frequency.

Unlike on SM8250, the L3 is voted through the L3_VOTE register, as the
downstream driver for this SoC does. The generic qcom,epss-l3 fallback
selects that, so no driver change is needed.

Assisted-by: LLM
Signed-off-by: Demeter Barna <me@xxxxxxxxxxxxxxxxxxx>
---
 arch/arm64/boot/dts/qcom/sm8350.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 55b32050c..52e8c2963 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/firmware/qcom,scm.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sm8350.h>
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/phy/phy-qcom-qmp.h>
@@ -3798,6 +3799,16 @@ apps_bcm_voter: bcm-voter {
 			};
 		};
 
+		epss_l3: interconnect@18590000 {
+			compatible = "qcom,sm8350-epss-l3", "qcom,epss-l3";
+			reg = <0 0x18590000 0 0x1000>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18591000 {
 			compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
 			reg = <0 0x18591000 0 0x1000>,

-- 
2.53.0