Re: [PATCH spi-next 04/11] spi: spi-fsl-lpspi: fsl_lpspi_set_watermark(): use FIELD_PREP() to encode FIFO Status register

[Marc Kleine-Budde]

On 16.03.2026 14:39:03, Mark Brown wrote:
> On Mon, Mar 16, 2026 at 09:39:05AM +0100, Marc Kleine-Budde wrote:
>
> > +#define FCR_RXWATER	GENMASK(18, 16)
> > +#define FCR_TXWATER	GENMASK(2, 0)

That's the width from the i.MX93 datasheet.

> The source of the watermark values appears to be
>
> 	temp = readl(fsl_lpspi->base + IMX7ULP_PARAM);
> 	fsl_lpspi->txfifosize = 1 << (temp & 0x0f);
> 	fsl_lpspi->rxfifosize = 1 << ((temp >> 8) & 0x0f);
>
> which suggests 4 bits of watermark not 3?  Or at least that something
> isn't joined up somewhere.

The param register's default value on the i.MX93 is:

| LPSPI1–LPSPI3:  0002_0303h
| LPSPI4:         0003_0303h
| LPSPI5–LPSPI8:  0002_0303h

This means a RX/TX-FIFO size of 1 << 3 == 8.

In the FCR register the RX/TX watermark are 3 bits. So this is
consistent.

On the imx7ulp and s32g2 the param gives 1 << 2 = 4 and the RX/TX
watermark are just 2 bits wide.


We can increase the the FCR_RXWATER and FCR_TXWATER to be 8 bits wide,
the rest of the register is reserved.

Marc

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