Re: [PATCH RFC v3 3/5] arm64: dts: qcom: nord-ride-embedded: Enable PCIe controllers and PHY

[Krishna Chaitanya Chundru]

On 10/21/2026 7:59 AM, Shawn Guo wrote:
> From: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
>
> The Nord Ride Embedded board routes all four PCIe links, so enable
> pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and
> describe the PERST# and WAKE# lines of each root port.
>
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@xxxxxxxxxxxxxxxx>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxxxxxxxx>
> Reviewed-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
> Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxxxxxxxx>
> Signed-off-by: Shawn Guo <shengchao.guo@xxxxxxxxxxxxxxxx>
> ---
>  .../boot/dts/qcom/nord-ride-embedded.dts      | 49 +++++++++++++++++++
>  1 file changed, 49 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
> index 49635695f832..fcc07226db8b 100644
> --- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
> +++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
> @@ -366,6 +366,55 @@ vreg_l3l_1p8: ldo3 {
>  	};
>  };
>  
> +&pcie_phy {
> +	vdda-phy-a-supply = <&vreg_l6a_1p2>;
> +	vdda-phy-b-supply = <&vreg_l4a_1p2>;
> +	vdda-phy-c-supply = <&vreg_l4a_1p2>;
> +	vdda-phy-d-supply = <&vreg_l4a_1p2>;
> +	vdda-pll-a-supply = <&vreg_l1e_0p9>;
Hi Shawn,

I did a mistake while sharing these changes, pll supply for b, c, d should be
l2e instead of l1e.
-    vdda-pll-b-supply = <&vreg_l1e_0p9>;
-    vdda-pll-c-supply = <&vreg_l1e_0p9>;
-    vdda-pll-d-supply = <&vreg_l1e_0p9>;
+    vdda-pll-b-supply = <&vreg_l2e_0p9>;
+    vdda-pll-c-supply = <&vreg_l2e_0p9>;
+    vdda-pll-d-supply = <&vreg_l2e_0p9>;

Can you update them as this patch is not applied yet.

- Krishna Chaitanya.
> +	vdda-pll-b-supply = <&vreg_l1e_0p9>;
> +	vdda-pll-c-supply = <&vreg_l1e_0p9>;
> +	vdda-pll-d-supply = <&vreg_l1e_0p9>;
> +
> +	status = "okay";
> +};
> +
> +&pcie0 {
> +	status = "okay";
> +};
> +
> +&pcie0_port0 {
> +	reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 0 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pcie1 {
> +	status = "okay";
> +};
> +
> +&pcie1_port0 {
> +	reset-gpios = <&tlmm 5 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pcie2 {
> +	status = "okay";
> +};
> +
> +&pcie2_port0 {
> +	reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
> +};
> +
> +&pcie3 {
> +	status = "okay";
> +};
> +
> +&pcie3_port0 {
> +	reset-gpios = <&tlmm 11 GPIO_ACTIVE_LOW>;
> +	wake-gpios = <&tlmm 9 GPIO_ACTIVE_LOW>;
> +};
> +
>  &qupv3_0 {
>  	firmware-name = "qcom/nord/qupv3fw.elf";
>