Re: [PATCH v2 06/10] iio: frequency: ad9910: add axi backend driver

[Nuno Sá]

On Thu, 22 Oct 2026 12:19:04 -0300, Rodrigo Alencar <rodrigo.alencar@xxxxxxxxxx> wrote:
> [...]
> length and duty offset programmed in SYNC_CLK cycles. The duty offset
> is realized by a delay applied once, before DRCTL starts toggling. The
> waveform is reprogrammed when the SYNC_CLK rate changes, so that the PWM
> output keeps its timing.
> 
> Signed-off-by: Rodrigo Alencar <rodrigo.alencar@xxxxxxxxxx>

Not more to add to Jonathan's feedback. But I do have a slight
preference for "FIELD_FIT() and reject it"

- Nuno Sá

-- 
Nuno Sá <nuno.sa@xxxxxxxxxx>