Re: [PATCH 2/2] Documentation: PCI: Document aer_inject's aer_mask_override parameter

[Daniel Pereira]

On Mon, Oct 26, 2026, Priyank Rathod wrote:
> The reason bit 26 reads 0b on the e1000e Endpoint in the cover letter
> is Note 3 of Table 7-149: a non-VF Function only implements bit 26 when
> Poisoned TLP Egress Blocking Supported is Set in the DPC Capability
> Register (Offset 04h, bit 6; PCIe r7.0, sec 7.9.14.2, Table 7-280).
> Per PCIe r7.0, sec 7.9.14, the DPC Extended Capability (001Dh) is only
> applicable to Root Ports and Switch Downstream Ports, not to Endpoints
> like e1000e (and in QEMU, pcie_aer_init() initializes PCI_ERR_UNCOR_MASK
> to PCI_ERR_UNC_INTN | PCI_ERR_UNC_TLPPRE = 0x02400000).

Hi Priyank,

Thank you for the detailed explanation, and for pointing me to Note 3 of
Table 7-149. That clears up why PCI_ERR_UNCOR_MASK reads 02400000 on the
e1000e in the sample session of the cover letter: bit 26 is only
implemented when the DPC capability reports Poisoned TLP Egress Blocking
support, which does not apply to an Endpoint.

> That said, your suggestion to use "Header Log Overflow or Internal
> Errors" (PCIe r7.0, sec 7.8.4.6, Table 7-152, bits 14-15, and
> sec 7.8.4.3, Table 7-149, bit 22) as the example is much clearer
> because those bits apply to Endpoints as well and match the sample
> output directly. If you or anyone else suggests the same, I will gladly
> change it.

Yes, I would suggest using those two in the example, since they are
masked by default on Endpoints too and match the sample output directly.
This is only a suggestion, of course; how to proceed is up to you and the
maintainers :)

Thanks,
Daniel