RE: [PATCH v2 1/1] PCI: hv: Spread load across CPUs when selecting effective affinity CPU

[Michael Kelley]

From: Naman Jain <namjain@xxxxxxxxxxxxxxxxxxx> Sent: Monday, October 26, 2026 1:56 AM
> 
> On 10/26/2026 10:29 AM, Michael Kelley wrote:
> 
> <snip>
> 
> > +/*
> > + * Track the count of SPIs assigned to each CPU. Pick a single CPU from the
> > + * affinity mask based on the SPI loading data, and have the parent IRQ
> > + * chip (should be "GICv3") set the effective affinity to that single CPU.
> > + */
> > +static int hv_pci_arm64_set_affinity(struct irq_data *d,
> > +				     const struct cpumask *mask_val,
> > +				     bool force)
> > +{
> > +	unsigned int cpu, prev_cpu;
> > +	int ret;
> > +
> > +	prev_cpu = cpumask_first(irq_data_get_effective_affinity_mask(d));
> > +
> > +	scoped_guard(raw_spinlock_irqsave, &cpu_spi_count_lock) {
> > +		if (prev_cpu < nr_cpu_ids)
> > +			hv_pci_dec_spi_count(d, prev_cpu);
> 
> Nit: Would it be better to add this nr_cpu_ids check in
> hv_pci_dec_spi_count()/hv_pci_inc_spi_count() instead? I don't have a
> strong opinion on it.

I like that suggestion. It drops 5 lines of code from the patch and
reduces clutter in the main code paths. I'll wait a couple of days to
see if there are any other comments, then spin a v3 with the change.

Michael

> 
> > +
> > +		if (force)
> > +			cpu = hv_pci_arm64_get_min_load(d, mask_val);
> > +		else
> > +			cpu = hv_pci_arm64_select_cpu(d, mask_val);
> > +
> > +		if (cpu >= nr_cpu_ids) {
> 
> At some places like this, you may still need to retain it.
> 
> > +			if (prev_cpu < nr_cpu_ids)
> > +				hv_pci_inc_spi_count(d, prev_cpu);
> > +			return -EINVAL;
> > +		}
> > +
> > +		hv_pci_inc_spi_count(d, cpu);
> > +	}
> > +
> > +	ret = irq_chip_set_affinity_parent(d, cpumask_of(cpu), force);
> > +	if (ret < 0) {
> > +		guard(raw_spinlock_irqsave)(&cpu_spi_count_lock);
> > +
> > +		if (prev_cpu < nr_cpu_ids)
> > +			hv_pci_inc_spi_count(d, prev_cpu);
> > +		if (cpu < nr_cpu_ids)
> > +			hv_pci_dec_spi_count(d, cpu);
> > +	}
> > +
> > +	return ret;
> 
> <snip>
> 
> With or without above nit changes, for the patch -
> 
> Reviewed-by: Naman Jain <namjain@xxxxxxxxxxxxxxxxxxx>
> Tested-by: Naman Jain <namjain@xxxxxxxxxxxxxxxxxxx>
> 
> Tested the patch on Azure ARM64 VM and verified the interrupt
> distribution and also saw soft lockups disappearing after optimal
> distribution of NVME - PCI interrupts produced by this patch.
> Not repeating here, observations are similar to what I mentioned in the
> review of v1.
> 
> Regards,
> Naman