[PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2

[H. Nikolaus Schaller]

Add the missing cpu_probe_ingenic cases for PRID_IMP_XBURST and
PRID_IMP_XBURST2_R2, which are used in Ingenic/Lumissil SoCs.

This correctly initializes the CPU type, write-combine behavior,
and CPU name string ("Ingenic XBurst" and "Ingenic XBurst II R2")
based on the processor ID.

Signed-off-by: H. Nikolaus Schaller <hns@xxxxxxxxxxxxx>
---
 arch/mips/kernel/cpu-probe.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 489612ed9d498..f4924c14bd735 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1768,6 +1768,13 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 
 	switch (c->processor_id & PRID_IMP_MASK) {
 
+	/* XBurst®1 with ISA */
+	case PRID_IMP_XBURST:
+		c->cputype = CPU_XBURST;
+		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+		__cpu_name[cpu] = "Ingenic XBurst";
+		break;
+
 	/* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */
 	case PRID_IMP_XBURST_REV1:
 
@@ -1828,6 +1835,13 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
 		__cpu_name[cpu] = "Ingenic XBurst II";
 		break;
 
+	/* XBurst®2 with MXU3.0 SIMD ISA */
+	case PRID_IMP_XBURST2_R2:
+		c->cputype = CPU_XBURST2;
+		c->writecombine = _CACHE_UNCACHED_ACCELERATED;
+		__cpu_name[cpu] = "Ingenic XBurst II R2";
+		break;
+
 	default:
 		panic("Unknown Ingenic Processor ID!");
 		break;
-- 
2.56.0