Re: [PATCH 2/2] Documentation: PCI: Document aer_inject's aer_mask_override parameter

[Daniel Pereira]

On Mon, Oct 12, 2026, Priyank Rathod wrote:
> To exercise the handling of such errors anyway, e.g., of those that are
> masked by default like Header Log Overflow or Poisoned TLP Egress
> Blocked, load the module with::

Hi Priyank,

I read the text against patch 1/2 and the current tree, and it matches
the implementation:

- the -EINVAL refusal for masked errors is the existing check in
aer_inject() for both the Correctable and the Uncorrectable case;
- 1/2 drops the writes to the hardware Mask registers, and
aer_inj_read_config() clears the pending injected bits from the Mask
values it returns;
- the hidden bits are kept set in dword writes through
uncor_mask_hidden/cor_mask_hidden until the module is unloaded;
- PCIEAER_INJECT is a tristate, so the boot parameter form applies when
it is built in.

The new section is also a proper subsection of "Software error
injection", and the documentation builds with it without new warnings.

There is one thing I could not reconcile, in case it is useful. The
text gives Poisoned TLP Egress Blocked as an example of an error that
is masked by default. In the sample session of the cover letter,
PCI_ERR_UNCOR_MASK of the e1000e reads 02400000 before the test, which
is PCI_ERR_UNC_INTN (0x00400000) plus PCI_ERR_UNC_TLPPRE (0x02000000),
while PCI_ERR_UNC_POISON_BLK (0x04000000) is clear. The vendor register
descriptions I found also list that bit with a reset value of 0. The
Correctable side does match: 0000c000 has Corrected Internal and Header
Log Overflow set. Internal errors match too, since
pci_aer_unmask_internal_errors() is only used for CXL.

Perhaps the example could name only errors whose default is confirmed,
for instance Header Log Overflow and the Internal Errors, or cite the
spec section if it does say that Poisoned TLP Egress Blocked is masked
by default. I may well be missing something in the spec.

Thanks,
Daniel