Re: [PATCH v2 5/7] arm64: dts: qcom: Add device tree for Lemans GearVM variant

[Deepti Jaggi]

On 10/14/2026 7:37 PM, Shawn Guo wrote:
> Add lemans-gearvm.dtsi for Lemans GearVM variant (SA8255P) that utilizes
> firmware to configure platform resources such as clocks, interconnects
> and TLMM.
> Device drivers request these resources through the SCMI power, reset and
> performance protocols.  Assign each device driver a dedicated SCMI
> channel and Tx/Rx doorbells to support parallel resource requests and
> aggregation in the SCMI platform server.  Operate the SCMI server stack
> in an SMP-enabled VM using the Qualcomm SMC/HVC transport driver for
> communication.
> 
> Group resource operations to improve abstraction and reduce the number of
> SCMI requests.  Follow the SCMI-based resource management approach
> demonstrated by Qualcomm at Linaro Connect 2024 [1].
> 
> [1] https://resources.linaro.org/en/resource/wfnfEwBhRjLV1PEAJoDDte
> 
> Co-developed-by: Shazad Hussain <shazad.hussain@xxxxxxxxxxxxxxxx>
> Signed-off-by: Shazad Hussain <shazad.hussain@xxxxxxxxxxxxxxxx>
> Signed-off-by: Nikunj Kela <quic_nkela@xxxxxxxxxxx>
> Co-developed-by: Deepti Jaggi <deepti.jaggi@xxxxxxxxxxxxxxxx>
> Signed-off-by: Deepti Jaggi <deepti.jaggi@xxxxxxxxxxxxxxxx>
> Signed-off-by: Shawn Guo <shengchao.guo@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi | 3232 +++++++++++++++++++
>  1 file changed, 3232 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
> 
> diff --git a/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi b/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
> new file mode 100644
> index 000000000000..4c155cbc7975
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/lemans-gearvm.dtsi
> @@ -0,0 +1,3232 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> + */
> +
> +#include "lemans.dtsi"
> +
> +/delete-node/ &xbl_boot_mem;
> +/delete-node/ &pil_adsp_mem;
> +/delete-node/ &q6_adsp_dtb_mem;
> +/delete-node/ &q6_gdsp0_dtb_mem;
> +/delete-node/ &pil_gdsp0_mem;
> +/delete-node/ &pil_gdsp1_mem;
> +/delete-node/ &q6_gdsp1_dtb_mem;
> +/delete-node/ &q6_cdsp0_dtb_mem;
> +/delete-node/ &pil_cdsp0_mem;
> +/delete-node/ &pil_gpu_mem;
> +/delete-node/ &q6_cdsp1_dtb_mem;
> +/delete-node/ &pil_cdsp1_mem;
> +/delete-node/ &pil_cvp_mem;
> +/delete-node/ &pil_video_mem;
> +/delete-node/ &scmi_mem;
> +/delete-node/ &firmware_reserved_mem;
> +
> +/ {
> +	clocks {
> +		bi_tcxo_div2: bi-tcxo-div2-clk {
> +			compatible = "fixed-factor-clock";
> +			clocks = <&xo_board_clk>;
> +			clock-mult = <1>;
> +			clock-div = <2>;
> +			#clock-cells = <0>;
> +		};
> +
> +		gpll0_board_clk: gpll0-board-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		sleep_clk: sleep-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +
> +		xo_board_clk: xo-board-clk {
> +			compatible = "fixed-clock";
> +			#clock-cells = <0>;
> +		};
> +	};
> +};
> +
> +&adreno_smmu {
> +	power-domains = <&scmi15_pd 0>;
> +};
> +
> +&cpufreq_hw {
> +	clocks = <&bi_tcxo_div2>, <&gpll0_board_clk>;
> +	clock-names = "xo", "alternate";
> +};
> +
> +&firmware {
> +	scm {
> +		memory-region = <&tz_ffi_mem>;
> +	};
> +
> +	scmi0: scmi-0 {
> +		compatible = "qcom,scmi-smc";
> +		arm,smc-id = <0xc6008012>;
> +		shmem = <&shmem0>;
> +

As bootloader updates the irq, we can add a comment here.

> +		interrupts = <GIC_SPI 963 IRQ_TYPE_EDGE_RISING>;
> +		interrupt-names = "a2p";
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		arm,max-msg = <10>;
> +		arm,max-msg-size = <256>;
> +		arm,max-rx-timeout-ms = <3000>;
> +
> +		status = "disabled";
> +
> +		scmi0_pd: protocol@11 {
> +			reg = <0x11>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		scmi0_dvfs: protocol@13 {
> +			reg = <0x13>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		scmi0_rst: protocol@16 {
> +			reg = <0x16>;
> +			#reset-cells = <1>;
> +		};
> +	};
> +
> +	scmi1: scmi-1 {
> +		compatible = "qcom,scmi-smc";
> +		arm,smc-id = <0xc6008012>;
> +		shmem = <&shmem1>;
> +
> +		interrupts = <GIC_SPI 964 IRQ_TYPE_EDGE_RISING>;
> +		interrupt-names = "a2p";
> +
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		arm,max-msg = <10>;
> +		arm,max-msg-size = <256>;
> +		arm,max-rx-timeout-ms = <3000>;

Thanks,
Deepti