Re: [PATCH 0/7] gpio: add Ambarella CV75 PL061 support

[Bartosz Golaszewski]

On Fri, 9 Oct 2026 12:57:53 +0200, Long Zhao via B4 Relay
<devnull+longzhao.ambarella.com@xxxxxxxxxx> said:
> Split from the combined CV75 bring-up series. These patches convert
> the ARM PL061 data path to regmap, then add the CV75 layout.
>
> Please take this series through the GPIO tree. The quirk, the PL061
> conversion and the Ambarella layout belong together.
>
> The GPIO driver does not depend on ARCH_AMBARELLA. The binding uses
> the ambarella vendor prefix, which is added by the SoC series and is
> not in mainline yet; dt_binding_check needs that prefix.
>
> GPIO data path uses gpio-regmap with two layouts (ARM PrimeCell and
> Ambarella). ARM PL061 sets GPIO_REGMAP_QUIRK_SET_AFTER_DIR. IRQ stays
> a custom PL061 irqchip. The linear domain is created with the PL061
> private data and attached by gpio-regmap. regmap-irq is not used.
>
> Tested on the CV75 EVK. The board boots. gpio-hammer toggles gpiochip0 line 26 ten times, and gpio-event-mon on line 27 records ten alternating rising and falling edges.
>
> Changes since the patches in the combined v9:
> - dt-bindings: explain that CV75 is a modified PL061 (Conor)
> - gpio-regmap: move quirks after fixed_direction_output (Andy)
> - gpio: pl061: use regmap_test_bits(), regmap_clear_bits() and
>   regmap_set_bits() for direction and interrupt enable (Andy).
>   The data register stays regmap_write(): regmap_set_bits() can
>   only set bits to 1, so it cannot drive a pin low.
> - gpio: pl061: add Ambarella register-layout variant: cache DAT
>   (REGCACHE_FLAT_S, not volatile) so gpio_set() does not
>   read-modify-write the pin level (Sashiko). Drop the Reviewed-by
>   from Andy and Linus on this commit; the code changed after
>   those tags.
>
> Link: https://patch.msgid.link/20261001-cv75-v5-v9-0-486cc289a4b8@xxxxxxxxxxxxx
>

Is this effectively a v10 of this series or something entirely new?

Bart