Re: [PATCH v4 0/6] drm/msm/dpu: rework layer mixer allocation and mode limits

[Dmitry Baryshkov]

On Thu, Oct 08, 2026 at 10:53:46PM +0530, Mahadevan P wrote:
> Currently, the DPU driver bases LM reservation off of the maximum
> supported width for the layer mixer and an arbitrary MAX_HDISPLAY_SPLIT.
> However, these limits are not hardware limits meaning that a single LM
> can support higher resolutions.
> 
> Switch to basing LM reservation off of PINGPONG and DSC encoder hardware
> limits.
> 
> This revision also adds clock-based mixer selection and a source-pipe
> width guard for mixers without source split.
> 
> Assisted-by: LLM
> Signed-off-by: Mahadevan P <mahadevan.p@xxxxxxxxxxxxxxxx>
> ---
> Changes in v4:
> - Rebased on msm-next, resolving conflicts.
> - Added clock-based mixer selection and reused the helper in mode
>   validation.
> - Added a source-pipe width guard for mixers without source split.
> - Extended the catalog cleanup to newer platforms.

What was the issue that caused display breakage on the CRD as reported
by Xilin Wu? How did you fix it?

> - Link to v3: https://lore.kernel.org/r/20260112-max-mixer-width-v3-0-f98063ea21f5@xxxxxxxxxxxxxxxx
> 

-- 
With best wishes
Dmitry