Re: [PATCH v2 3/4] dt-bindings: mmc: cdns,sd6hc: add SD6HC DDR50 read-path tuning

[Krzysztof Kozlowski]

On Fri, Oct 09, 2026 at 10:14:50AM +0800, tze.yee.ng@xxxxxxxxxx wrote:
> From: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>
> 
> DDR50 has no CMD19 tuning, so the SD6HC read path must be centred by
> static, board/SoC-characterised PHY settings. Add three optional SD6HC
> properties for the extended-read DDR modes (SD DDR50 and eMMC DDR52):
> 
>   - cdns,ddr-read-dqs-delay-ps: read-DQS delay in picoseconds that centres
>     the read eye (default 0).
>   - cdns,ddr-no-lpbk-dqs:       disable the loopback DQS read strobe and
>     use the fabricated phony DQS instead. Loopback DQS is the recommended
>     default; set this only on boards that need the phony DQS read path.
>   - cdns,ddr-phony-dqs-timing:  PHY_CTRL[9:4] phony DQS assertion timing.
>     The driver derives this from the RE# pulse width; this property
>     overrides the computed value for boards whose flight time shifts the
>     DDR data return.
> 
> Signed-off-by: Tze Yee Ng <tze.yee.ng@xxxxxxxxxx>
> ---
> Changes in v2:
> - Retitled to "dt-bindings: mmc: cdns,sd6hc:". (Tanmay Kathpalia)
> - Renamed cdns,ddr50-* -> cdns,ddr-*. (Tanmay Kathpalia)
> - cdns,ddr-read-dqs-delay-ps is now in picoseconds. (Krzysztof Kozlowski)
> - Replaced the read-DQS source selector with a cdns,ddr-no-lpbk-dqs
>   boolean. (Krzysztof Kozlowski)
> - Reworded the phony-dqs-timing text. (Krzysztof Kozlowski, 
>   Tanmay Kathpalia)
> - Dropped the SD4HC note. (Tanmay Kathpalia)
> - Scope the new properties to the extended-read DDR modes (DDR50 and
>   DDR52). (Tanmay Kathpalia)

There are no lore links in the cover letter to previous versions and b4
diff fails.

b4 diff 'cover.1791459448.git.tze.yee.ng@xxxxxxxxxx'
Looking up cover.1791459448.git.tze.yee.ng@xxxxxxxxxx
Checking for older revisions
Grabbing search results from lore.kernel.org
---
Analyzing 5 messages in the thread
Could not find lower series to compare against.

Why aren't you using b4 to send patches? Why making it difficult for us?

> ---
>  .../devicetree/bindings/mmc/cdns,sd6hc.yaml   | 30 +++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml b/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml
> index d5ea2717904b..911ce58f8dab 100644
> --- a/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/cdns,sd6hc.yaml
> @@ -74,6 +74,36 @@ properties:
>      maximum: 1000
>      default: 24
>  
> +  cdns,ddr-read-dqs-delay-ps:
> +    description: >
> +      Read-DQS delay (DLL_SLAVE[7:0]) in picoseconds that centres the read
> +      eye in the extended-read DDR modes (SD DDR50, eMMC DDR52), which have
> +      no CMD19 tuning. The PHY runs the DLL bypassed in these modes, so the
> +      driver converts this to delay elements (divided by
> +      cdns,delay-element-ps). The 8-bit field holds at most 255 elements;
> +      larger values are clamped to that limit.
> +    minimum: 0

Drop, 0 is the default.

Where is the maximum value?

> +    default: 0
> +
> +  cdns,ddr-no-lpbk-dqs:
> +    description: >

Drop > everywhere

Best regards,
Krzysztof