Re: [PATCH v6 4/6] alpha: decode and acknowledge Tsunami system machine checks

[Matt Turner]

> +#include <asm/irq_regs.h>
>  #include <asm/core_tsunami.h>

Patch 1 already includes this a few lines down, so it is now included
twice.

> +     /* INV invalidates SYN, CMD and ADDR; SERR has no command/address. */
> +     if (perror & (TSUNAMI_PERROR_INV | perror_m_serr)) {

If SERR is set together with another error bit, this throws away the
transaction that the other error latched. Can it test for SERR being
the only error bit?

Similarly, with an ECC bit and a PCI bit both set, the fields are
decoded as ECC. We cannot tell which came first, but a comment saying
so would help.

> +     tsunami_clear_errors(&live);

This runs for every vector, and tsunami_report_live_errors() then
prints whatever was latched. Does a PERROR bit still latch when its
PERRMASK bit is clear? If it does, NDS left over from config probing
will show up at KERN_CRIT on an unrelated CPU error.

> +             tsunami_process_logout_frame(header, 1);
> +             dik_show_regs(get_irq_regs(), NULL);

For the correctable vector this is a full register dump per CRE. Titan
only does it under alpha_verbose_mcheck. The old code dumped as well,
so it is not a regression, but would you want the same gate for 620?

> +             mb();
> +     }
>
> -     process_mcheck_info(vector, la_ptr, "TSUNAMI",
> -                         mcheck_expected(smp_processor_id()));
>  }

This leaves a blank line before the closing brace until patch 6.