Re: [PATCH 05/11] dt-bindings: clock: qcom: ipq5332-gcc: Describe clock inputs per compatible

[Krzysztof Kozlowski]

On 21/09/2026 08:19, Kathiravan Thirumoorthy wrote:
> The IPQ5332 and IPQ5424 GCC blocks use different clock input orderings.
> Document the clock inputs in compatible-specific schema constraints instead
> of using a common clock description.
> 
> Also add the 375 MHz PPE clock generated by the CMN PLL to the IPQ5424
> clock input list.
> 
> This keeps the binding aligned with the clock ordering used by the
> existing DTS and GCC driver implementations.
> 
> Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@xxxxxxxxxxxxxxxx>
> ---
>  .../bindings/clock/qcom,ipq5332-gcc.yaml           | 26 +++++++++++++---------
>  1 file changed, 16 insertions(+), 10 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> index 1230183fc0a9..fb39dffca988 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml
> @@ -25,14 +25,7 @@ properties:
>  
>    clocks:
>      minItems: 5
> -    items:
> -      - description: Board XO clock source
> -      - description: Sleep clock source
> -      - description: PCIE 2lane PHY pipe clock source
> -      - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
> -      - description: USB PCIE wrapper pipe clock source
> -      - description: PCIE 2-lane PHY2 pipe clock source
> -      - description: PCIE 2-lane PHY3 pipe clock source


You are changing the order which is ABI break. Describe the actual
problem to justify such change. Are you saying this was broken since
beginning or what exactly is not working here? The driver was added by
Qualcomm in 2024, so how did it even work? It's not some 10 yo legacy
where we did some mistakes in binding while converting from TXT.

Also, I do not get why the list cannot be shared.

Best regards,
Krzysztof