[PATCH 2/3] PCI: tegra194: Avoid full Endpoint reinit on PERST#

[Manikanta Maddireddy]

Tegra194 and Tegra234 Endpoint mode receive PERST# as a fundamental
reset. Controller registers are lost across that reset, but DWC
Endpoint resources live for the controller lifetime.

Use the DWC init-or-reinit helper for Tegra PERST# deassertions so only
reset-lost registers are restored after the first initialization. Keep
the EPF deinit notification in the deassert path where refclk and core
reset are available.

Signed-off-by: Manikanta Maddireddy <mmaddireddy@xxxxxxxxxx>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 513299541f18..dd3f4c30ba52 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1914,7 +1914,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 
 	/* Perform cleanup that requires refclk and core reset deasserted */
 	pci_epc_deinit_notify(pcie->pci.ep.epc);
-	dw_pcie_ep_cleanup(&pcie->pci.ep);
 
 	val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 	val &= ~PORT_LOGIC_SPEED_CHANGE;
@@ -1958,7 +1957,7 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
 	val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
 	dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
 
-	ret = dw_pcie_ep_init_registers(ep);
+	ret = dw_pcie_ep_init_or_reinit_registers(ep);
 	if (ret) {
 		dev_err(dev, "Failed to complete initialization: %d\n", ret);
 		goto fail_init_complete;
-- 
2.34.1