Re: [RFC PATCH 2/4] spi: cadence-xspi: add ACMD support for SPI NAND

[Fei Xie]

Hi Mark,

Thanks for the review.

I agree that the controller should not interpret the child driver's
private data and that this dependency should be removed.

The difficulty is that the hardware ACMD sequencer needs the complete
multi-operation sequence to be described before it is started. For
example, the SPI NAND core currently submits PAGE READ, status polling
and READ CACHE as separate spi_mem_exec_op() calls. The STIG path can
execute those operations individually, while the ACMD hardware combines
them into one programmed sequence.

Would an SPI-mem operation-sequence interface be a reasonable direction
to explore? The NAND core could describe the ordered operations and
polling condition, and the controller could either execute the sequence
in hardware or fall back to the existing individual operations. This
would keep NAND-specific knowledge out of the controller driver.

I would appreciate your guidance on the interface direction before
reworking the implementation for v2.

The implementation issues you identified, including use of the interrupt
callback, timeout cleanup, DMA handling and short transfers, will also be
addressed in the next revision.

Thanks,
Fei