[PATCH v2 6/7] arm64: dts: qcom: hawi: add iris video codec node
From: Wangao Wang
Date: Tue Sep 22 2026 - 23:30:42 EST
Add the iris video codec device node for the hawi SoC, describing the
register space, interrupt, nine power domains (including the
VPU5x-specific mm-int and cx-int domains), thirteen clocks, two
interconnect paths for CPU config and video memory bandwidth, IOMMU
mappings, and the operating point table covering 150 MHz through 1000 MHz.
Signed-off-by: Wangao Wang <wangao.wang@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/hawi.dtsi | 155 +++++++++++++++++++++++++++++++++++++
1 file changed, 155 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/hawi.dtsi b/arch/arm64/boot/dts/qcom/hawi.dtsi
index c7ae8133b9cdc88133f6dccdf87bfa8bc88677e1..dbd13c9aa10fb4230c226a207b278e8ca698a92a 100644
--- a/arch/arm64/boot/dts/qcom/hawi.dtsi
+++ b/arch/arm64/boot/dts/qcom/hawi.dtsi
@@ -3421,6 +3421,161 @@ ice: crypto@1d88000 {
power-domains = <&gcc GCC_UFS_PHY_GDSC>;
};
+ iris: video-codec@2000000 {
+ compatible = "qcom,hawi-iris";
+ reg = <0x0 0x02000000 0x0 0xf0000>;
+
+ interrupts = <GIC_ESPI 238 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
+ <&videocc VIDEO_CC_MVS0_GDSC>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc VIDEO_CC_MVS0_VPP0_GDSC>,
+ <&videocc VIDEO_CC_MVS0_VPP1_GDSC>,
+ <&videocc VIDEO_CC_MVS0A_GDSC>,
+ <&videocc VIDEO_CC_MM_INT_GDSC>,
+ <&videocc VIDEO_CC_AXI0_CX_INT_GDSC>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vpp0",
+ "vpp1",
+ "apv",
+ "mm-int",
+ "cx-int";
+
+ clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
+ <&gcc GCC_VIDEO_AXI0C_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CLK>,
+ <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0C_CTL_FREERUN_CLK>,
+ <&videocc VIDEO_CC_MVS0C_DEBUG_CLK>,
+ <&videocc VIDEO_CC_CX_AXI0_CLK>,
+ <&videocc VIDEO_CC_MVS0_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP0_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP1_CLK>,
+ <&videocc VIDEO_CC_MVS0_VPP0_VPP1_GATING_CLK>,
+ <&videocc VIDEO_CC_MVS0A_CLK>,
+ <&videocc VIDEO_CC_MVS0B_CLK>;
+ clock-names = "iface",
+ "ifacec",
+ "core",
+ "core_freerun",
+ "core_ctl_freerun",
+ "core_debug",
+ "cx_iface",
+ "vcodec0_core",
+ "vcodec_vpp0",
+ "vcodec_vpp1",
+ "vcodec_vpp0_vpp1_gating",
+ "vcodec_apv",
+ "vcodec_bse";
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_IRIS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ memory-region = <&video_mem>;
+
+ resets = <&gcc GCC_VIDEO_AXI0C_CLK_ARES>,
+ <&videocc VIDEO_CC_MVS0C_CTL_FREERUN_CLK_ARES>;
+ reset-names = "bus0",
+ "core";
+
+ dma-coherent;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x0 0x0 0x0 0xffc00000>;
+
+ status = "disabled";
+
+ iris_non_pixel: non-pixel {
+ iommus = <&apps_smmu 0x1540 0x0000>,
+ <&apps_smmu 0x1620 0x0000>,
+ <&apps_smmu 0x1544 0x0000>;
+ iommu-ranges = <0x32000000 0xcdc00000>;
+ };
+
+ iris_pixel: pixel {
+ iommus = <&apps_smmu 0x1543 0x0000>;
+ };
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000 150000000
+ 150000000 225000000>;
+ required-opps = <&rpmhpd_opp_low_svs_d2>,
+ <&rpmhpd_opp_low_svs_d2>;
+ };
+
+ opp-285000000 {
+ opp-hz = /bits/ 64 <285000000 240000000
+ 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs_d0>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000
+ 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_low_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-420000000 {
+ opp-hz = /bits/ 64 <420000000 420000000
+ 420000000 630000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000
+ 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-560000000 {
+ opp-hz = /bits/ 64 <560000000 533000000
+ 533000000 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-630000000 {
+ opp-hz = /bits/ 64 <630000000 630000000
+ 630000000 1104000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000 710000000
+ 710000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000 710000000
+ 850000000 1260000000>;
+ required-opps = <&rpmhpd_opp_turbo>,
+ <&rpmhpd_opp_turbo_l3>;
+ };
+ };
+ };
+
videocc: clock-controller@20f0000 {
compatible = "qcom,hawi-videocc";
reg = <0x0 0x020f0000 0x0 0x10000>;
--
2.43.0