Re: [PATCH v13 3/5] PCI/ACPI: Tidy _OSC control bit checking
From: Rafael J. Wysocki (Intel)
Date: Tue Sep 22 2026 - 09:53:14 EST
On Sat, Sep 19, 2026 at 6:27 PM Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx> wrote:
>
> Add OSC_OWNER() helper to prettify checking the _OSC control bits to learn
> whether the platform has granted us control of PCI features. No functional
> change intended.
>
> [bhelgaas: split to separate patch, commit log]
> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx>
> Signed-off-by: Bjorn Helgaas <bhelgaas@xxxxxxxxxx>
Acked-by: Rafael J. Wysocki (Intel) <rafael@xxxxxxxxxx>
> ---
> Changes since v12
>
> * Rebased to v7.3-rc3. Parenthesized the OSC_OWNER() arguments, as
> checkpatch --strict asks.
> * Also convert native_cxl_error, which v12 left open coded. Its bit comes
> from the extended control word, so that word gets its own ext_ctrl
> local.
>
> v12 posting
> https://lore.kernel.org/all/20201126011816.711106-1-helgaas@xxxxxxxxxx/
>
> drivers/acpi/pci_root.c | 37 ++++++++++++++++++++++---------------
> 1 file changed, 22 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index 88c65f34e305..756dc2f055f5 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -993,6 +993,12 @@ static void acpi_pci_root_release_info(struct pci_host_bridge *bridge)
> __acpi_pci_root_release_info(bridge->release_data);
> }
>
> +#define OSC_OWNER(ctrl, bit, flag) \
> + do { \
> + if (!((ctrl) & (bit))) \
> + flag = 0; \
> + } while (0)
> +
> struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> struct acpi_pci_root_ops *ops,
> struct acpi_pci_root_info *info,
> @@ -1003,6 +1009,7 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> int node = acpi_get_node(device->handle);
> struct pci_bus *bus;
> struct pci_host_bridge *host_bridge;
> + u32 ctrl, ext_ctrl;
>
> info->root = root;
> info->bridge = device;
> @@ -1028,21 +1035,21 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> goto out_release_info;
>
> host_bridge = to_pci_host_bridge(bus->bridge);
> - if (!(root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL))
> - host_bridge->native_pcie_hotplug = 0;
> - if (!(root->osc_control_set & OSC_PCI_SHPC_NATIVE_HP_CONTROL))
> - host_bridge->native_shpc_hotplug = 0;
> - if (!(root->osc_control_set & OSC_PCI_EXPRESS_AER_CONTROL))
> - host_bridge->native_aer = 0;
> - if (!(root->osc_control_set & OSC_PCI_EXPRESS_PME_CONTROL))
> - host_bridge->native_pme = 0;
> - if (!(root->osc_control_set & OSC_PCI_EXPRESS_LTR_CONTROL))
> - host_bridge->native_ltr = 0;
> - if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
> - host_bridge->native_dpc = 0;
> -
> - if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
> - host_bridge->native_cxl_error = 0;
> +
> + ctrl = root->osc_control_set;
> + ext_ctrl = root->osc_ext_control_set;
> +
> + OSC_OWNER(ctrl, OSC_PCI_EXPRESS_NATIVE_HP_CONTROL,
> + host_bridge->native_pcie_hotplug);
> + OSC_OWNER(ctrl, OSC_PCI_SHPC_NATIVE_HP_CONTROL,
> + host_bridge->native_shpc_hotplug);
> + OSC_OWNER(ctrl, OSC_PCI_EXPRESS_AER_CONTROL, host_bridge->native_aer);
> + OSC_OWNER(ctrl, OSC_PCI_EXPRESS_PME_CONTROL, host_bridge->native_pme);
> + OSC_OWNER(ctrl, OSC_PCI_EXPRESS_LTR_CONTROL, host_bridge->native_ltr);
> + OSC_OWNER(ctrl, OSC_PCI_EXPRESS_DPC_CONTROL, host_bridge->native_dpc);
> +
> + OSC_OWNER(ext_ctrl, OSC_CXL_ERROR_REPORTING_CONTROL,
> + host_bridge->native_cxl_error);
>
> acpi_dev_power_up_children_with_adr(device);
>
> --
> 2.43.0
>