Re: [PATCH v2 0/5] PCI: qcom: Add PCIe support for Shikra SoC
From: Sushrut Shree Trivedi
Date: Mon Sep 21 2026 - 10:27:59 EST
On 9/2/2026 2:16 PM, Konrad Dybcio wrote:
On 8/31/26 9:26 AM, Sushrut Shree Trivedi wrote:My bad; I did ACK Mani's comment in v1 regarding higher voltage corner votes.
Add PCIe support for Shikra target, by adding dt-bindings for phy,You also silently adjusted the OPP levels in the DT patch:
controller and corresponding phy & controller drivers/device-tree
changes.
Shikra RC is connected to TC9563 PCIe switch on all three
EVK variants: CQS, CQM and IQS. The individual downstream ports
of TC9563 connect like below:
DSP1: M.2 B-Key for 5G Modem
DSP2: M.2 M-Key for NVMe
DSP3: Embedded ethernet device
Power and reset to M.2 B and M.2 M slot are controlled via
TC9563 GPIO's. Since TC9563 GPIO driver from Alex is still
under active review, current series only contains basic PCIe
enablement for the controller / PHY. TC9563 enablement changes
would be posted as a separate series once the GPIO driver is
ready.
[1] https://lore.kernel.org/all/e2inl7k5gsjj6oomv2k5ximuzpb3gfiz66ufet3b4hvov7zqt4@qz4pifbos7yf/
Signed-off-by: Sushrut Shree Trivedi <sushrut.trivedi@xxxxxxxxxxxxxxxx>
---
Changes in v2:
- Remove TC9563 specific changes [Mani]
- Fix commit descriptions/subjects [Bjorn Helgaas]
- Fix PCIe controller dt-binding errors [Krzysztof Kozlowski / Mani]
- Document PCIe Gen2 limitation in controller node & commit msg [Konrad Dybcio / Mani]
- Add GCC_PCIE_SLEEP_CLK (which is actually PHY AUX CLK) in PCIe PHY
node.
Will mention in cover letter next time onwards.
Yes, Gen2 can be supported with low svs corner as per HW team.
< + required-opps = <&rpmpd_opp_nom>;
---
+ required-opps = <&rpmpd_opp_low_svs>;
is the lower one suitable?
Konrad