[PATCH v2 2/2] ARM: dts: imx50: add support for Amazon Kindle 4 (Yoshi)

[Andrii Salivon]

Add initial device tree for the Amazon Kindle 4 non-touch e-reader
(codename "yoshi", mainboard marked E01100), based on the i.MX50 SoC.

This enables the console (UART1) and internal eMMC (eSDHC3), tested
booting to a full Arch Linux ARM userspace with systemd on real
hardware.

Signed-off-by: Andrii Salivon <andrijsalivon@xxxxxxxxx>
---
 arch/arm/boot/dts/nxp/imx/Makefile            |  1 +
 .../boot/dts/nxp/imx/imx50-amazon-yoshi.dts   | 59 +++++++++++++++++++
 2 files changed, 60 insertions(+)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx50-amazon-yoshi.dts

diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index 1a2539fa19b4..1a9e70b985d6 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -23,6 +23,7 @@ dtb-$(CONFIG_SOC_IMX35) += \
 	imx35-eukrea-mbimxsd35-baseboard.dtb \
 	imx35-pdk.dtb
 dtb-$(CONFIG_SOC_IMX50) += \
+	imx50-amazon-yoshi.dtb \
 	imx50-evk.dtb \
 	imx50-kobo-aura.dtb
 dtb-$(CONFIG_SOC_IMX51) += \
diff --git a/arch/arm/boot/dts/nxp/imx/imx50-amazon-yoshi.dts b/arch/arm/boot/dts/nxp/imx/imx50-amazon-yoshi.dts
new file mode 100644
index 000000000000..417972ad6bb3
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx50-amazon-yoshi.dts
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/dts-v1/;
+#include "imx50.dtsi"
+
+/ {
+	model = "Amazon Kindle 4 (Yoshi)";
+	compatible = "amazon,yoshi", "fsl,imx50";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@70000000 {
+		device_type = "memory";
+		reg = <0x70000000 0x10000000>;
+	};
+};
+
+&esdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_sd3>;
+	bus-width = <8>;
+	non-removable;
+	min-frequency = <400000>;
+	max-frequency = <40000000>;
+	disable-wp;
+	status = "okay";
+
+	/* Internal eMMC */
+};
+
+&iomuxc {
+	pinctrl_sd3: sd3grp {
+		fsl,pins = <
+			MX50_PAD_SD3_CMD__ESDHC3_CMD		0x1e4
+			MX50_PAD_SD3_CLK__ESDHC3_CLK		0xd4
+			MX50_PAD_SD3_D0__ESDHC3_DAT0		0x1d4
+			MX50_PAD_SD3_D1__ESDHC3_DAT1		0x1d4
+			MX50_PAD_SD3_D2__ESDHC3_DAT2		0x1d4
+			MX50_PAD_SD3_D3__ESDHC3_DAT3		0x1d4
+			MX50_PAD_SD3_D4__ESDHC3_DAT4		0x1d4
+			MX50_PAD_SD3_D5__ESDHC3_DAT5		0x1d4
+			MX50_PAD_SD3_D6__ESDHC3_DAT6		0x1d4
+			MX50_PAD_SD3_D7__ESDHC3_DAT7		0x1d4
+		>;
+	};
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX50_PAD_UART1_TXD__UART1_TXD_MUX	0x1e4
+			MX50_PAD_UART1_RXD__UART1_RXD_MUX	0x1e4
+		>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
-- 
2.55.0