Re: [PATCH 2/4] arm64: dts: qcom: nord: Add iris video node

[Shawn Guo]

On Sat, Sep 19, 2026 at 10:14:56AM +0530, Vishnu Reddy wrote:
> Add iris video codec to nord SoC, which comes with significantly different
> powering up sequence than previous platforms, thus different clocks and
> resets.
> 
> Signed-off-by: Vishnu Reddy <busanna.reddy@xxxxxxxxxxxxxxxx>
> ---
>  arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 114 ++++++++++++++++++++++++++++
>  1 file changed, 114 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> index 74f4e6be8652..03f827f3e5fc 100644
> --- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
> @@ -1428,6 +1428,120 @@ camcc: clock-controller@9ce0000 {
>  		#power-domain-cells = <1>;
>  	};
>  
> +	iris: video-codec@aa00000 {
> +		compatible = "qcom,nord-iris", "qcom,glymur-iris";
> +		reg = <0x0 0x0aa00000 0x0 0xf0000>;

nord-embedded.dtsi is a place to accommodate Nord Embedded variant
specific resource descriptions, like clock, regulator, pinctrl,
interconnect, power domain, PHY, etc. The rest of descriptions should
go to nord.dtsi, like reg, interrupts, iommu, dma, etc.

Shawn

> +
> +		clocks = <&nwgcc NW_GCC_VIDEO_AXI0_CLK>,
> +			 <&videocc VIDEO_CC_MVS0C_CLK>,
> +			 <&videocc VIDEO_CC_MVS0_CLK>,
> +			 <&nwgcc NW_GCC_VIDEO_AXI0C_CLK>,
> +			 <&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
> +			 <&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
> +			 <&nwgcc NW_GCC_VIDEO_AXI1_CLK>,
> +			 <&videocc VIDEO_CC_MVS1_CLK>,
> +			 <&videocc VIDEO_CC_MVS1_FREERUN_CLK>;
> +		clock-names = "core_iface",
> +			      "core",
> +			      "vcodec0_core",
> +			      "vcodec0_iface",
> +			      "core_freerun",
> +			      "vcodec0_core_freerun",
> +			      "vcodec1_iface",
> +			      "vcodec1_core",
> +			      "vcodec1_core_freerun";
> +
> +		dma-coherent;
> +
> +		interconnects = <&hscnoc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
> +				 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
> +				<&mmss_noc MASTER_VIDEO_MVP0 QCOM_ICC_TAG_ALWAYS
> +				 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> +		interconnect-names = "cpu-cfg",
> +				     "video-mem";
> +
> +		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		memory-region = <&video_mem>;
> +
> +		operating-points-v2 = <&iris_opp_table>;
> +
> +		power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
> +				<&videocc VIDEO_CC_MVS0_GDSC>,
> +				<&rpmhpd RPMHPD_MXC>,
> +				<&rpmhpd RPMHPD_MMCX>,
> +				<&videocc VIDEO_CC_MVS1_GDSC>;
> +		power-domain-names = "venus",
> +				     "vcodec0",
> +				     "mxc",
> +				     "mmcx",
> +				     "vcodec1";
> +
> +		resets = <&nwgcc NW_GCC_VIDEO_AXI0_CLK_ARES>,
> +			 <&nwgcc NW_GCC_VIDEO_AXI0C_CLK_ARES>,
> +			 <&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
> +			 <&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>,
> +			 <&nwgcc NW_GCC_VIDEO_AXI1_CLK_ARES>,
> +			 <&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>;
> +		reset-names = "core_bus",
> +			      "vcodec0_bus",
> +			      "core",
> +			      "vcodec0_core",
> +			      "vcodec1_bus",
> +			      "vcodec1_core";
> +
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		dma-ranges = <0x0 0x0 0x0 0xffe00000>;
> +
> +		status = "disabled";
> +
> +		non-pixel {
> +			iommus = <&apps_smmu_1 0x0940 0x20>,
> +				 <&apps_smmu_1 0x0944 0x0>,
> +				 <&apps_smmu_1 0x0960 0x20>;
> +			iommu-ranges = <0x25800000 0xda600000>;
> +		};
> +
> +		pixel {
> +			iommus = <&apps_smmu_1 0x0943 0x0>;
> +		};
> +
> +		iris_opp_table: opp-table {
> +			compatible = "operating-points-v2";
> +
> +			opp-240000000 {
> +				opp-hz = /bits/ 64 <240000000 240000000 360000000>;
> +				required-opps = <&rpmhpd_opp_svs>,
> +						<&rpmhpd_opp_svs>;
> +			};
> +
> +			opp-435000000 {
> +				opp-hz = /bits/ 64 <435000000 435000000 652500000>;
> +				required-opps = <&rpmhpd_opp_svs_l1>,
> +						<&rpmhpd_opp_svs_l1>;
> +			};
> +
> +			opp-480000000 {
> +				opp-hz = /bits/ 64 <480000000 480000000 720000000>;
> +				required-opps = <&rpmhpd_opp_svs_l1>,
> +						<&rpmhpd_opp_nom>;
> +			};
> +
> +			opp-533333333 {
> +				opp-hz = /bits/ 64 <533333333 533333333 800000000>;
> +				required-opps = <&rpmhpd_opp_svs_l1>,
> +						<&rpmhpd_opp_turbo>;
> +			};
> +
> +			opp-560000000 {
> +				opp-hz = /bits/ 64 <560000000 560000000 840000000>;
> +				required-opps = <&rpmhpd_opp_nom>,
> +						<&rpmhpd_opp_turbo_l1>;
> +			};
> +		};
> +	};
> +
>  	videocc: clock-controller@aaf0000 {
>  		compatible = "qcom,nord-videocc";
>  		reg = <0x0 0x0aaf0000 0x0 0x10000>;
> 
> -- 
> 2.34.1
> 
>