Re: [PATCH RESEND v4 0/3] x86/apic: Add support for additional AMD EILVT registers

[Ravi Bangoria]

Hi Boris,

On 15-Sep-26 5:59 AM, Borislav Petkov wrote:
> On Thu, Sep 03, 2026 at 02:58:38PM +0530, Naveen N Rao (AMD) wrote:
>> Add support for additional APIC EILVT registers being introduced in 
>> future AMD processors:
>> https://docs.amd.com/v/u/en-US/69205_1.00_AMD64_IBS_PUB)
>>
>> This is a resend of v4, rebased on tip/master. Previous posting:
>> http://lore.kernel.org/r/cover.1784785046.git.naveen@xxxxxxxxxx
>>
>> Since then:
>> - I have retained the macro name 'APIC_EILVT_NR_AMD_10H' since I felt it 
>>   is accurate, and didn't hear a preference for anything else. Happy to 
>>   change if needed (Ingo)
>> - I have gone through Sashiko's findings on the previous versions, and 
>>   none of those justified a change. Other than the pre-existing issues
>>   reported by Sashiko, there have been 3 findings:
> 
> Except that someone should address the preexisting issues before we pile more
> ontop:
> 
> https://sashiko.dev/#/patchset/cover.1788425679.git.naveen%40kernel.org

All the preexisting IBS issues reported by Sashiko there are applicable only
for the very old family 0x10 AMD processors. Given that, it may not be worth
addressing them unless someone is actually running into the issue in practice.

Thanks,
Ravi