[PATCH iwl-net 1/2] ice: fix DPLL registration on boards without the SMA clock mux

[Petr Oros]

The SMA and U.FL connectors of an E810-C timing board are routed by a
PCA9575 GPIO expander, and ice_dpll_init_info_sw_pins() reaches it
through ice_read_sma_ctrl(). On a board that carries a CGU but no such
expander the netlist lookup fails with -ENXIO, which aborts
ice_dpll_init_info() and with it the whole DPLL registration:

  ice 0000:cc:00.0: ice_dpll_init_info - fail: d->inputs:...
  ice 0000:cc:00.0: DPLLs init failure err:-6

Userspace loses the EEC and PPS devices, every CGU pin and the recovered
clock pin.

The netlist describes the mux with a clock mux node, which
ice_init_feature_support() already turns into ICE_F_SMA_CTRL. Key the
software controlled pins on that flag. Without the mux the SMA wrappers
stay inputs, the state the mux path programs at init anyway, and do not
advertise DIRECTION_CAN_CHANGE. The U.FL pins are the other leg of the
mux, so they are hidden, and the outgoing CGU pins stay visible as
REF-SMA1 and REF-SMA2/U.FL2.

The layout is not exotic, the E810_C827_SyncE_SFP_SEC configuration in
Intel's 4.80 NVM package has no clock mux node either. Such boards
worked until the SMA and U.FL redesign moved the expander access into
the DPLL init path.

Fixes: 2dd5d03c77e2 ("ice: redesign dpll sma/u.fl pins control")
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Petr Oros <poros@xxxxxxxxxx>
---
 drivers/net/ethernet/intel/ice/ice_dpll.c | 20 +++++++++++++++++---
 1 file changed, 17 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/intel/ice/ice_dpll.c b/drivers/net/ethernet/intel/ice/ice_dpll.c
index 85a74cd6ea1f3e..e0362b6bf332e5 100644
--- a/drivers/net/ethernet/intel/ice/ice_dpll.c
+++ b/drivers/net/ethernet/intel/ice/ice_dpll.c
@@ -107,6 +107,9 @@ static const struct dpll_pin_frequency ice_esync_range[] = {
  */
 static bool ice_dpll_is_sw_pin(struct ice_pf *pf, u8 index, bool input)
 {
+	if (!input && !ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
+		return false;
+
 	if (input && pf->hw.device_id == ICE_DEV_ID_E810C_QSFP)
 		index -= ICE_DPLL_SW_PIN_INPUT_BASE_QSFP -
 			 ICE_DPLL_SW_PIN_INPUT_BASE_SFP;
@@ -1213,6 +1216,8 @@ static int ice_dpll_sma_direction_set(struct ice_dpll_pin *p,
 
 	if (p->direction == direction && p->active)
 		return 0;
+	if (!ice_is_feature_supported(p->pf, ICE_F_SMA_CTRL))
+		return -EOPNOTSUPP;
 	ret = ice_read_sma_ctrl(&p->pf->hw, &data);
 	if (ret)
 		return ret;
@@ -4510,9 +4515,14 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 						  true, &freq_supp_num);
 		pin->prop.freq_supported_num = freq_supp_num;
 		pin->prop.capabilities =
-			(DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE |
-			 DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE |
-			 caps);
+			(DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE | caps);
+		if (ice_is_feature_supported(pf, ICE_F_SMA_CTRL)) {
+			pin->prop.capabilities |=
+				DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
+		} else {
+			pin->active = true;
+			pin->direction = DPLL_PIN_DIRECTION_INPUT;
+		}
 		pin->pf = pf;
 		pin->prop.board_label = ice_dpll_sw_pin_sma[i];
 		pin->input = &d->inputs[pin_abs_idx];
@@ -4526,6 +4536,7 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 		pin->idx = i;
 		pin->prop.type = DPLL_PIN_TYPE_EXT;
 		pin->prop.capabilities = caps;
+		pin->hidden = !ice_is_feature_supported(pf, ICE_F_SMA_CTRL);
 		pin->pf = pf;
 		pin->prop.board_label = ice_dpll_sw_pin_ufl[i];
 		if (i == ICE_DPLL_PIN_SW_1_IDX) {
@@ -4555,6 +4566,9 @@ static int ice_dpll_init_info_sw_pins(struct ice_pf *pf)
 		ice_dpll_phase_range_set(&pin->prop.phase_range, phase_adj_max);
 	}
 
+	if (!ice_is_feature_supported(pf, ICE_F_SMA_CTRL))
+		return 0;
+
 	/* Initialize the SMA control register to a known-good default state.
 	 * Without this write the PCA9575 GPIO expander retains its power-on
 	 * default (all outputs high) which makes all SW pins appear inactive.
-- 
2.55.0