Re: [PATCH v3 0/9] perf/x86: Don't write PEBS_ENABLED on KVM transitions

[Peter Zijlstra]

On Thu, Sep 10, 2026 at 10:56:44AM -0700, Sean Christopherson wrote:
> On Thu, Aug 06, 2026, Sean Christopherson wrote:
> > On Fri, May 08, 2026, Sean Christopherson wrote:
> > > Sean Christopherson (9):
> > >   perf/x86/intel: Ensure guest PEBS path doesn't set unwanted
> > >     PERF_GLOBAL_CTRL bits
> > >   perf/x86/intel: Don't write PEBS_ENABLED on host<=>guest xfers if CPU
> > >     has isolation
> > >   perf/x86/intel: Don't context switch DS_AREA (and PEBS config) if PEBS
> > >     is unused
> > >   perf/x86/intel: Make @data a mandatory param for
> > >     intel_guest_get_msrs()
> > >   perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask
> > >   perf/x86: KVM: Have perf define a dedicated struct for getting guest
> > >     PEBS data
> > >   perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM
> > >   KVM: VMX: Drop a redundant pmu->global_ctrl check when processing
> > >     pebs_enable
> > >   KVM: VMX: Only tell perf to enable PEBS counters for fully enabled
> > >     PMCs
> > > 
> > >  arch/x86/events/core.c            |  5 +-
> > >  arch/x86/events/intel/core.c      | 92 +++++++++++++++++++------------
> > >  arch/x86/events/intel/lbr.c       |  2 +-
> > >  arch/x86/events/perf_event.h      |  7 ++-
> > >  arch/x86/include/asm/kvm_host.h   |  9 ---
> > >  arch/x86/include/asm/perf_event.h | 11 +++-
> > >  arch/x86/kvm/vmx/pmu_intel.c      | 28 +++++++---
> > >  arch/x86/kvm/vmx/vmx.c            | 10 ++--
> > >  arch/x86/kvm/vmx/vmx.h            | 15 ++++-
> > >  9 files changed, 114 insertions(+), 65 deletions(-)
> > 
> > Ping.  This still applies on Linus' tree and against tip/master.
> 
> Ping again.  This fixes a real issue and IMO provides much-needed improvements
> for the KVM<=>perf APIs.

Right, finally got around to staring at them. How did you want them
merged?

AFAICT 2-4 have Fixes tags and should go in perf/urgent, while the rest
goes in perf/core?

/me tries and finds patch 5 doesn't apply.