[PATCH v11 1/9] dt-bindings: media: qcom,glymur-iris: Add glymur video codec
From: Vishnu Reddy
Date: Thu Sep 17 2026 - 01:02:12 EST
Add device tree binding for the Qualcomm Glymur Iris video codec. Glymur
is a new generation of video IP that introduces a dual-core architecture.
The second core brings its own power domain, clocks, and reset lines,
requiring additional power domains and clocks in the power sequence. The
current maxItems constraints for clocks, power-domains and non-pixel
iommus in the common venus schema were sized for platforms available at
the time of authoring. The glymur platform introduces a dual core
architecture that requires more clocks and power domains, exceeding these
limits. Raise maxItems for clocks, clock-names, power-domains,
power-domain-names and non-pixel iommus to accommodate glymur platform.
The glymur platform specific schema have fixed constraints for these
properties, so the common schema only acts as an upper bound. Since the
common schema now only acts as an upper bound, add explicit maxItems
overrides for the non-pixel iommus in the qcom,sm8550-iris and
qcom,sm8750-iris schemas to keep the fixed constraints as before.
Signed-off-by: Vishnu Reddy <busanna.reddy@xxxxxxxxxxxxxxxx>
---
.../bindings/media/qcom,glymur-iris.yaml | 218 +++++++++++++++++++++
.../bindings/media/qcom,sm8550-iris.yaml | 6 +
.../bindings/media/qcom,sm8750-iris.yaml | 6 +
.../bindings/media/qcom,venus-common.yaml | 11 +-
4 files changed, 236 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
new file mode 100644
index 000000000000..de4792f3b658
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,glymur-iris.yaml
@@ -0,0 +1,218 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,glymur-iris.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Glymur SoC Iris video encoder and decoder
+
+maintainers:
+ - Vishnu Reddy <busanna.reddy@xxxxxxxxxxxxxxxx>
+
+description:
+ The Iris video processing unit on Qualcomm Glymur SoC is a video encode and
+ decode accelerator.
+
+properties:
+ compatible:
+ const: qcom,glymur-iris
+
+ clocks:
+ maxItems: 9
+
+ clock-names:
+ items:
+ - const: core_iface
+ - const: core
+ - const: vcodec0_core
+ - const: vcodec0_iface
+ - const: core_freerun
+ - const: vcodec0_core_freerun
+ - const: vcodec1_iface
+ - const: vcodec1_core
+ - const: vcodec1_core_freerun
+
+ dma-coherent: true
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: cpu-cfg
+ - const: video-mem
+
+ non-pixel:
+ type: object
+ properties:
+ iommus:
+ maxItems: 3
+
+ operating-points-v2: true
+ opp-table:
+ type: object
+
+ power-domains:
+ maxItems: 5
+
+ power-domain-names:
+ items:
+ - const: venus
+ - const: vcodec0
+ - const: mxc
+ - const: mmcx
+ - const: vcodec1
+
+ resets:
+ maxItems: 6
+
+ reset-names:
+ items:
+ - const: core_bus
+ - const: vcodec0_bus
+ - const: core
+ - const: vcodec0_core
+ - const: vcodec1_bus
+ - const: vcodec1_core
+
+required:
+ - clocks
+ - clock-names
+ - compatible
+ - dma-coherent
+ - interconnects
+ - interconnect-names
+ - power-domains
+ - power-domain-names
+ - resets
+ - reset-names
+
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+
+ video-codec@aa00000 {
+ compatible = "qcom,glymur-iris";
+ reg = <0x0aa00000 0xf0000>;
+
+ clocks = <&gcc_video_axi0c_clk>,
+ <&videocc_mvs0c_clk>,
+ <&videocc_mvs0_clk>,
+ <&gcc_video_axi0_clk>,
+ <&videocc_mvs0c_freerun_clk>,
+ <&videocc_mvs0_freerun_clk>,
+ <&gcc_video_axi1_clk>,
+ <&videocc_mvs1_clk>,
+ <&videocc_mvs1_freerun_clk>;
+ clock-names = "core_iface",
+ "core",
+ "vcodec0_core",
+ "vcodec0_iface",
+ "core_freerun",
+ "vcodec0_core_freerun",
+ "vcodec1_iface",
+ "vcodec1_core",
+ "vcodec1_core_freerun";
+
+ dma-coherent;
+
+ interconnects = <&hsc_noc_master_appss_proc &config_noc_slave_venus_cfg>,
+ <&mmss_noc_master_video &mc_virt_slave_ebi1>;
+ interconnect-names = "cpu-cfg",
+ "video-mem";
+
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+
+ memory-region = <&video_mem>;
+
+ operating-points-v2 = <&iris_opp_table>;
+
+ power-domains = <&videocc_mvs0c_gdsc>,
+ <&videocc_mvs0_gdsc>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>,
+ <&videocc_mvs1_gdsc>;
+ power-domain-names = "venus",
+ "vcodec0",
+ "mxc",
+ "mmcx",
+ "vcodec1";
+
+ resets = <&gcc_video_axi0c_clk_ares>,
+ <&gcc_video_axi0_clk_ares>,
+ <&videocc_mvs0c_freerun_clk_ares>,
+ <&videocc_mvs0_freerun_clk_ares>,
+ <&gcc_video_axi1_clk_ares>,
+ <&videocc_mvs1_freerun_clk_ares>;
+ reset-names = "core_bus",
+ "vcodec0_bus",
+ "core",
+ "vcodec0_core",
+ "vcodec1_bus",
+ "vcodec1_core";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ dma-ranges = <0x0 0x0 0xffe00000>;
+
+ non-pixel {
+ iommus = <&apps_smmu 0x1940 0x0000>,
+ <&apps_smmu 0x1944 0x0000>,
+ <&apps_smmu 0x19e0 0x0000>;
+ iommu-ranges = <0x25800000 0xda600000>;
+ };
+
+ pixel {
+ iommus = <&apps_smmu 0x1943 0x0000>;
+ };
+
+ video-firmware {
+ iommus = <&apps_smmu 0x19e2 0x0000>;
+ };
+
+ iris_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-240000000 {
+ opp-hz = /bits/ 64 <240000000 240000000 360000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-338000000 {
+ opp-hz = /bits/ 64 <338000000 338000000 507000000>;
+ required-opps = <&rpmhpd_opp_svs>,
+ <&rpmhpd_opp_svs>;
+ };
+
+ opp-366000000 {
+ opp-hz = /bits/ 64 <366000000 366000000 549000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-444000000 {
+ opp-hz = /bits/ 64 <444000000 444000000 666000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_nom>;
+ };
+
+ opp-533333334 {
+ opp-hz = /bits/ 64 <533333334 533333334 800000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>,
+ <&rpmhpd_opp_turbo>;
+ };
+
+ opp-655000000 {
+ opp-hz = /bits/ 64 <655000000 655000000 982000000>;
+ required-opps = <&rpmhpd_opp_nom>,
+ <&rpmhpd_opp_turbo_l1>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
index 6ee9d23554cf..81d35be565f9 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml
@@ -81,6 +81,12 @@ properties:
iommus:
maxItems: 2
+ non-pixel:
+ type: object
+ properties:
+ iommus:
+ maxItems: 1
+
dma-coherent: true
memory-region:
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml
index b6d5ded1aae6..6c1ed1b9fdde 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml
@@ -43,6 +43,12 @@ properties:
iommus:
maxItems: 2
+ non-pixel:
+ type: object
+ properties:
+ iommus:
+ maxItems: 1
+
operating-points-v2: true
opp-table:
type: object
diff --git a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml
index 68d5e592a028..03b8b8992624 100644
--- a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml
@@ -20,11 +20,11 @@ properties:
clocks:
minItems: 3
- maxItems: 7
+ maxItems: 9
clock-names:
minItems: 3
- maxItems: 7
+ maxItems: 9
firmware-name:
maxItems: 1
@@ -41,11 +41,11 @@ properties:
power-domains:
minItems: 1
- maxItems: 4
+ maxItems: 5
power-domain-names:
minItems: 1
- maxItems: 4
+ maxItems: 5
'#address-cells':
const: 1
@@ -64,7 +64,8 @@ properties:
properties:
iommus:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
iommu-ranges:
maxItems: 1
required:
--
2.34.1