Re: [PATCH 1/2] arm64: dts: qcom: nord: add GPI DMA controller nodes
From: Shawn Guo
Date: Wed Sep 16 2026 - 23:47:00 EST
On Wed, Sep 16, 2026 at 05:55:38PM +0200, Bartosz Golaszewski wrote:
> Add GPI DMA controller nodes for all three QUPv3 engines.
>
> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/nord.dtsi | 67 ++++++++++++++++++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/nord.dtsi b/arch/arm64/boot/dts/qcom/nord.dtsi
> index 22c026c32fb5..870033a106db 100644
> --- a/arch/arm64/boot/dts/qcom/nord.dtsi
> +++ b/arch/arm64/boot/dts/qcom/nord.dtsi
> @@ -3,6 +3,7 @@
> * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
> */
>
> +#include <dt-bindings/dma/qcom-gpi.h>
Nit: this include should probably go with patch 2/2? Or could these two
patches be squashed?
Shawn
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> #include <dt-bindings/soc/qcom,gpr.h>
> @@ -1062,6 +1063,28 @@ soc: soc@0 {
> dma-ranges = <0 0 0 0 0x10 0>;
> ranges = <0 0 0 0 0x10 0>;
>
> + gpi_dma2: dma-controller@800000 {
> + compatible = "qcom,nord-gpi-dma", "qcom,sm6350-gpi-dma";
> + reg = <0x0 0x00800000 0x0 0x60000>;
> + #dma-cells = <3>;
> + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <12>;
> + dma-channel-mask = <0xfff>;
> + iommus = <&apps_smmu_0 0x15b6 0x0>;
> + status = "disabled";
> + };
> +
> qupv3_2: geniqup@8c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0x0 0x008c0000 0x0 0x2000>;
> @@ -1260,6 +1283,28 @@ uart20: serial@898000 {
> };
> };
>
> + gpi_dma0: dma-controller@900000 {
> + compatible = "qcom,nord-gpi-dma", "qcom,sm6350-gpi-dma";
> + reg = <0x0 0x00900000 0x0 0x60000>;
> + #dma-cells = <3>;
> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <12>;
> + dma-channel-mask = <0xfff>;
> + iommus = <&apps_smmu_2 0x1016 0x0>;
> + status = "disabled";
> + };
> +
> qupv3_0: geniqup@9c0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0x0 0x009c0000 0x0 0x2000>;
> @@ -1431,6 +1476,28 @@ uart5: serial@994000 {
> };
> };
>
> + gpi_dma1: dma-controller@a00000 {
> + compatible = "qcom,nord-gpi-dma", "qcom,sm6350-gpi-dma";
> + reg = <0x0 0x00a00000 0x0 0x60000>;
> + #dma-cells = <3>;
> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
> + dma-channels = <12>;
> + dma-channel-mask = <0xfff>;
> + iommus = <&apps_smmu_2 0x1056 0x0>;
> + status = "disabled";
> + };
> +
> qupv3_1: geniqup@ac0000 {
> compatible = "qcom,geni-se-qup";
> reg = <0x0 0x00ac0000 0x0 0x2000>;
>
> --
> 2.47.3
>
>