Re: [PATCH RESEND v4 1/2] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock

[AngeloGioacchino Del Regno]

On Wed, 16 Sep 2026 11:59:51 +0800, Chen-Yu Tsai wrote:
> The MFG_ASYNC domain, which is likely associated to the whole MFG block,
> currently specifies clk26m as its domain clock. This is bogus, since the
> clock is an external crystal with no controls. Also, the MFG block has
> a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
> diagram, gates access to the hardware registers. Having this one as the
> domain clock makes much more sense. This also fixes access to the MFGTOP
> registers.
> 
> [...]

Applied to v7.3-next/dts64, thanks!

[1/2] arm64: dts: mediatek: mt8173: Fix MFG_ASYNC power domain clock
      commit: c9b3c82c9f1f86cdb2449d47e4ca66a19159ee12
[2/2] arm64: dts: mediatek: mt8173: Add GPU device nodes
      commit: f0d8c2b05e2d384c0162b41d3728433c1bb23972

Cheers,
Angelo