[PATCH] clk: qcom: gcc-ipq5424: Fix TME reset register offsets

[Abel Vesa]

The GCC_TME_BCR and GCC_TME_SEC_BUS_BCR offsets exceed the regmap maximum
of 0x3f024. Regmap therefore rejects accesses to both registers, leaving
the resets ineffective while the reset operations report success.

The offsets appear to contain typographical errors. Use 0x10000 for
GCC_TME_BCR, matching the offset used on IPQ9574 and the surrounding
register layout. Use 0x1a030 for GCC_TME_SEC_BUS_BCR, placing it in the
same register block as GCC_SEC_CTRL_BCR at 0x1a000.

Fixes: 21b5d5a4a311 ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5424 SoC")
Assisted-by: LLM
Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>
---
The replacement offsets are inferred from the register layout and the
IPQ9574 driver;

Sricharan, could you please confirm both offsets, particularly 0x1a030
for GCC_TME_SEC_BUS_BCR?
---
 drivers/clk/qcom/gcc-ipq5424.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/gcc-ipq5424.c b/drivers/clk/qcom/gcc-ipq5424.c
index 3ddd4b3aedea..32243e110b27 100644
--- a/drivers/clk/qcom/gcc-ipq5424.c
+++ b/drivers/clk/qcom/gcc-ipq5424.c
@@ -2949,7 +2949,7 @@ static const struct qcom_reset_map gcc_ipq5424_resets[] = {
 	[GCC_QUPV3_SPI0_BCR] = { 0x04000, 0 },
 	[GCC_QUPV3_SPI1_BCR] = { 0x05000, 0 },
 	[GCC_IMEM_BCR] = { 0x0e000, 0 },
-	[GCC_TME_BCR] = { 0x100000, 0 },
+	[GCC_TME_BCR] = { 0x10000, 0 },
 	[GCC_DDRSS_BCR] = { 0x11000, 0 },
 	[GCC_PRNG_BCR] = { 0x13020, 0 },
 	[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },
@@ -2960,7 +2960,7 @@ static const struct qcom_reset_map gcc_ipq5424_resets[] = {
 	[GCC_UNIPHY2_BCR] = { 0x17064, 0 },
 	[GCC_WCSS_BCR] = { 0x18004, 0 },
 	[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },
-	[GCC_TME_SEC_BUS_BCR] = { 0xa1030, 0 },
+	[GCC_TME_SEC_BUS_BCR] = { 0x1a030, 0 },
 	[GCC_ADSS_BCR] = { 0x1c000, 0 },
 	[GCC_LPASS_BCR] = { 0x27000, 0 },
 	[GCC_PCIE0_BCR] = { 0x28000, 0 },

---
base-commit: e6e35979777d646fe3c7c94dca7dd32fb25d45f4
change-id: 20260916-clk-qcom-gcc-ipq5424-fix-tme-bcrs-offsets-ed5288607211

Best regards,
--  
Abel Vesa <abel.vesa@xxxxxxxxxxxxxxxx>