Re: [PATCH v2 3/7] arm64: dts: freescale: Add Lino iMX93

[Francesco Dolcini]

Hello Andrew,
thanks a lot for the detailed explanation.

On Tue, Sep 15, 2026 at 09:57:56PM +0200, Andrew Lunn wrote:
> > Would you mind to articulate in which situation such race condition can
> > happen?
> 
> Most PHYs have a number of interrupt sources. Taking a random example:
> 
> /* DM9161 Interrupt Register */

...

> The interrupt line is still low, indicating a link interrupt, but
> without an edge, no interrupt handler is triggered. The interrupt has
> been lost, and the link is reported down, despite being up.
> 
> If however you are using level interrupts, as soon as the interrupt
> handler exits, and reenables the interrupt in the parent interrupt
> controller, it fires again, and the link interrupt is handled.
> 
> If you have multiple interrupts indicated by a single line, you should
> use level handling in the parent interrupt controller.

I looked into the specific ethernet phy used here, TI DP83867, and
I would say that the falling edge interrupt should be safe on this
specific board/phy.

There is a single ISR register, and it's a single read/clear atomic
operation (MII_DP83867_ISR 0x13, dp83867_ack_interrupt).  This is done
before doing any access to any other register, so the interrupt will
just fires again if anything happen. I do not see the race condition window.

I know it is not conclusive, but we have multiple boards with the
same edge interrupt configuration and the same ethernet phy (the
interrupt is wired directly to a TI SoC, that supports only edge
interrupt, not to a gpio expander) and we never had any failure. Our
test coverage is quite good IMO, commit 91a7cda1f4b8 ("net: phy: Fix
race condition on link status change") is something I did because our
testing had some sporadic failures for a different race condition.

What do you think? *IF* my reasoning is correct I would suggest to keep
the code as it is now.

Francesco