[PATCH 18/31] arm64: dts: qcom: sm8650: Add domain idle state names
From: Maulik Shah
Date: Mon Sep 14 2026 - 03:04:29 EST
Add the idle-state-name property for the domain idle state so low power
modes are described consistently and its name is printed in pmdomain
debugfs.
While at it, update CPU idle state names to match the low power modes
they describe.
Use little, big, and prime CPU idle state labels for consistency with
other platforms using this CPU naming scheme.
Signed-off-by: Maulik Shah <maulik.shah@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/sm8650.dtsi | 30 ++++++++++++++++--------------
1 file changed, 16 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
index 99509305f970..11e491acb715 100644
--- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
@@ -451,9 +451,9 @@ core7 {
idle-states {
entry-method = "psci";
- silver_cpu_sleep_0: cpu-sleep-0-0 {
+ little_cpu_sleep_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
- idle-state-name = "silver-rail-power-collapse";
+ idle-state-name = "silver-pll-pc";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <550>;
exit-latency-us = <750>;
@@ -461,9 +461,9 @@ silver_cpu_sleep_0: cpu-sleep-0-0 {
local-timer-stop;
};
- gold_cpu_sleep_0: cpu-sleep-1-0 {
+ big_cpu_sleep_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
- idle-state-name = "gold-rail-power-collapse";
+ idle-state-name = "gold-pll-rail-pc";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <600>;
exit-latency-us = <1300>;
@@ -471,9 +471,9 @@ gold_cpu_sleep_0: cpu-sleep-1-0 {
local-timer-stop;
};
- gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
+ prime_cpu_sleep_0: cpu-sleep-2-0 {
compatible = "arm,idle-state";
- idle-state-name = "gold-plus-rail-power-collapse";
+ idle-state-name = "goldplus-pll-rail-pc";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <500>;
exit-latency-us = <1350>;
@@ -485,6 +485,7 @@ gold_plus_cpu_sleep_0: cpu-sleep-2-0 {
domain-idle-states {
cluster_sleep_0: cluster-sleep-0 {
compatible = "domain-idle-state";
+ idle-state-name = "l3-pc";
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <750>;
exit-latency-us = <2350>;
@@ -493,6 +494,7 @@ cluster_sleep_0: cluster-sleep-0 {
cluster_sleep_1: cluster-sleep-1 {
compatible = "domain-idle-state";
+ idle-state-name = "llcc-off";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2800>;
exit-latency-us = <4400>;
@@ -1659,49 +1661,49 @@ psci {
cpu_pd0: power-domain-cpu0 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&silver_cpu_sleep_0>;
+ domain-idle-states = <&little_cpu_sleep_0>;
};
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&silver_cpu_sleep_0>;
+ domain-idle-states = <&little_cpu_sleep_0>;
};
cpu_pd2: power-domain-cpu2 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&gold_cpu_sleep_0>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd3: power-domain-cpu3 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&gold_cpu_sleep_0>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd4: power-domain-cpu4 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&gold_cpu_sleep_0>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd5: power-domain-cpu5 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&gold_cpu_sleep_0>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd6: power-domain-cpu6 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&gold_cpu_sleep_0>;
+ domain-idle-states = <&big_cpu_sleep_0>;
};
cpu_pd7: power-domain-cpu7 {
#power-domain-cells = <0>;
power-domains = <&cluster_pd>;
- domain-idle-states = <&gold_plus_cpu_sleep_0>;
+ domain-idle-states = <&prime_cpu_sleep_0>;
};
cluster_pd: power-domain-cluster {
--
2.43.0