Re: [PATCH v2 0/3] Fix three racy updates to MSR_K7_HWCR

[Jim Mattson]

On Fri, Jun 12, 2026 at 4:01 PM Andrew Cooper <andrew.cooper3@xxxxxxxxxx> wrote:
>
> > hoists the HWCR update logic out
> > into a new helper, amd_update_hwcr(), which performs the read-modify-write
> > with interrupts disabled
>
> Add some `perf` to your test scenario and these bugs will reappear, this
> time caused by NMIs.
>
> I don't have any good suggestions. Core scope MSRs are horrible because
> you can't update them atomically.

I agree, but I spot-checked a couple of (Zen1+) PPRs, and I thought
they said that HWCR has thread scope. For example, in
https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/56255_OSRR.pdf
has:

> _lthree[1:0]_core[3:0]_thread[1:0]; MSRC0010015

And, earlier:

> The absence of the instance parameter _thread[1:0] signifies that there is not a specific instance of said register per thread and thus the register is shared between thread 1 and thread 0.

Was it core-shared on older platforms?