Re: [PATCH v4 07/13] clk: qcom: dispcc-qcm2290: Update GDSC *wait_val values and flags

[Dmitry Baryshkov]

On Thu, Jun 04, 2026 at 10:56:13AM +0530, Imran Shaik wrote:
> Update the QCM2290 DISPCC GDSC wait_val fields to match the hardware
> default values. Incorrect settings can cause the GDSC FSM to stuck,
> leading to power on/off failures. And update GDSC flags to retain the
> registers, and poll for the CFG GDSCR, and switch between HW/SW mode
> dynamically as per the latest convention.

Too many ands for one patch. Zero explanation (other than 'latest
convention'. Which convention? The flags describe hardware behaviour,
not conventions).

> 
> Signed-off-by: Imran Shaik <imran.shaik@xxxxxxxxxxxxxxxx>
> ---
>  drivers/clk/qcom/dispcc-qcm2290.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c
> index f5dbd19d0a0334362a44f91a69229cb0f018f309..4c1eef79f41b6907fe79f2b18bcb5f6160c74a43 100644
> --- a/drivers/clk/qcom/dispcc-qcm2290.c
> +++ b/drivers/clk/qcom/dispcc-qcm2290.c
> @@ -468,11 +468,14 @@ static const struct qcom_reset_map disp_cc_qcm2290_resets[] = {
>  
>  static struct gdsc mdss_gdsc = {
>  	.gdscr = 0x3000,
> +	.en_rest_wait_val = 0x2,
> +	.en_few_wait_val = 0x2,
> +	.clk_dis_wait_val = 0xf,
>  	.pd = {
>  		.name = "mdss_gdsc",
>  	},
>  	.pwrsts = PWRSTS_OFF_ON,
> -	.flags = HW_CTRL,
> +	.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
>  };
>  
>  static struct gdsc *disp_cc_qcm2290_gdscs[] = {
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry