Re: [PATCH v8 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver

[Vladimir Zapolskiy]

On 6/4/26 00:12, Bryan O'Donoghue wrote:
> On 03/06/2026 21:42, Vladimir Zapolskiy wrote:
> > > > Split configurations explicitly use other lanes for clocks. E.g. check
> > > > the RB5 Navigation schematics, CAM0B connector.
> > > Can you please check:
> > >
> > > CSI_3PHASE_COMMON.CSI_COMMON_CTRL5
> > >
> > > 0 LN0_PWRDN_B Lane 0
> > > ...
> > > 7 LNCK_PWRDN_B Clock Lane
> > Please note that media devices have a numeration scheme of lanes starting
> > from 1 (it'd be easy to check/confirm it), for instance today CAMSS has
> > lane numeration starting from 0 is out of the accepted scheme, and here
> > it'd be better to correct it and not enter the same pit.
>
> Yes fair point CAMSS has done this wrong since forever. data-lanes = <1
> 2 3 4> => LN0, LN1, LN2, LN3>
> > I don't have access to the IP spec, anyway I do not grasp it, where are
> > 8 lanes on the CSIPHY found? Each CSIPHY IP has 4+1 D-PHY lanes, not 8.
>
> Max CSI2 data-lanes is 8
>
> #define V4L2_MBUS_CSI2_MAX_DATA_LANES          8

Judging by the name that's something V4L2 or in other words software
specific, while I do reference to the actual pads of Qualcomm SoCs,
and I do not see 8 differential pairs per a CSIPHY, but only 5 lanes.

If that's correct, the data/clock lane numbers should lay in 1 to 5 range.

> That doesn't really explain why this register has seven data-lanes and
> one-clock lane.
>
> It just is what it is.

--
Best wishes,
Vladimir