[PATCH v3 2/5] dt-bindings: clock: versal-clk: Fix mio_clk index range in clock-names pattern
From: Michal Simek
Date: Wed Jun 03 2026 - 11:55:15 EST
The clock-names pattern "^mio_clk[00-77]+.*$" was intended to constrain
the MIO index to the valid range 00..77 (ZynqMP has 78 MIO pins),
but a regex character class cannot express a multi-digit decimal range.
Replace the bogus character class with an explicit alternation that
enumerates the two-digit decimal values 00..77.
Fixes: 03d4a1004053 ("dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml")
Signed-off-by: Michal Simek <michal.simek@xxxxxxx>
---
Changes in v3:
- New patch in series
Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
index bef109d163a8..d843d95801b5 100644
--- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml
@@ -116,7 +116,7 @@ allOf:
- const: pss_alt_ref_clk
- const: aux_ref_clk
- const: gt_crx_ref_clk
- - pattern: "^mio_clk[00-77]+.*$"
+ - pattern: "^mio_clk(0[0-9]|[1-6][0-9]|7[0-7])+.*$"
- pattern: "gem[0-3]+_emio_clk.*$"
- pattern: "swdt[0-1]+_ext_clk.*$"
--
2.43.0