Re: [PATCH RESEND v4 0/8] can: flexcan: Add NXP S32N79 SoC support

[Bough Chen]

On Wed, Jun 03, 2026 at 09:13:34AM +0200, Ciprian Costea wrote:
> From: Ciprian Marian Costea <ciprianmarian.costea@xxxxxxxxxxx>
> 
> This patch series adds FlexCAN support for the NXP S32N79 SoC.
> 
> The S32N79 is an automotive-grade processor from NXP with multiple
> FlexCAN instances. The FlexCAN IP integration on S32N79 differs from
> other SoCs in the interrupt routing - it uses two separate interrupt
> lines:
>   - one interrupt for mailboxes 0-127
>   - one interrupt for bus error detection and device state changes
> 
> The CAN controllers are connected through an irqsteer interrupt
> controller in the RCU (Resource Control Unit) domain.
> 
> This series:
>   1. Splits flexcan_irq() into dedicated handlers for multi-IRQ platforms
>   2. Adds dt-bindings documentation for S32N79 FlexCAN
>   3. Introduces FLEXCAN_QUIRK_IRQ_BERR to handle the two-interrupt
>      configuration
>   4. Adds S32N79 device data and compatible string to the driver
>   5. Adds FlexCAN device tree nodes for S32N79 SoC
>   6. Enables FlexCAN devices on the S32N79-RDB board
> 
> Tested on S32N79-RDB board with CAN and CAN FD communication.

Tested on imx95-19x19-evk board with CAN and CAN FD communication. No issue found.
This means this patch set do not impact the original platforms.

For this patch set, feel free to add tag:
Reviewed-and-tested-by: Haibo Chen <haibo.chen@xxxxxxx>

Regards
Haibo Chen
> 
> This is a resend of v4 with no changes.
> 
> v4 -> v3
> - flexcan_chip_interrupts_enable(): disable/enable all IRQ lines
>   (not just dev->irq) during IMASK register writes
> - Split rx/tx masks per mailbox IRQ line (struct flexcan_mb_irq) so
>   each handler on S32G2 only processes its own MB range
> - Added received Acked-by tag on DT bindings patch
> 
> v3 -> v2
> - Split flexcan_irq() into dedicated handlers (flexcan_irq_mb,
>   flexcan_irq_boff, flexcan_irq_berr) to fix duplicate event
>   processing when multiple IRQ lines run concurrently (new patch).
> - Added flexcan_irq_esr() handler composing state + berr for S32N79
> - Ordered quirks used by s32n devtype data by value.
> 
> v2 -> v1
> - Renamed FLEXCAN_QUIRK_NR_IRQ_2 to FLEXCAN_QUIRK_IRQ_BERR to better
> describe the actual hardware feature
> - Appended new quirk at the end
> - Switched from platform_get_irq to platform_get_irq_byname usage
> - Updated interrupt description in dt-bindings
> 
> Ciprian Marian Costea (8):
>   can: flexcan: use dedicated IRQ handlers for multi-IRQ platforms
>   can: flexcan: disable all IRQ lines in
>     flexcan_chip_interrupts_enable()
>   can: flexcan: split rx/tx masks per mailbox IRQ line
>   dt-bindings: can: fsl,flexcan: add NXP S32N79 SoC support
>   can: flexcan: add FLEXCAN_QUIRK_IRQ_BERR quirk
>   can: flexcan: add NXP S32N79 SoC support
>   arm64: dts: s32n79: add FlexCAN nodes
>   arm64: dts: s32n79: enable FlexCAN devices
> 
>  .../bindings/net/can/fsl,flexcan.yaml         |  30 ++-
>  arch/arm64/boot/dts/freescale/s32n79-rdb.dts  |  12 +
>  arch/arm64/boot/dts/freescale/s32n79.dtsi     |  50 ++++
>  drivers/net/can/flexcan/flexcan-core.c        | 249 +++++++++++++++---
>  drivers/net/can/flexcan/flexcan.h             |  12 +-
>  5 files changed, 316 insertions(+), 37 deletions(-)
> 
> -- 
> 2.43.0
>