RE: [PATCH v17 00/17] Add Renesas RZ/G3L SD/eMMC support

From: Biju Das

Date: Wed Jun 03 2026 - 03:22:57 EST


Hi all,

Please ignore this series as by mistake instead of patch series 2
I mentioned it as Patch series 17.

I will fix the issue soon.

Sorry for the inconvenience.

Cheers,
Biju

> -----Original Message-----
> From: Biju <biju.das.au@xxxxxxxxx>
> Sent: 03 June 2026 07:57
> Subject: [PATCH v17 00/17] Add Renesas RZ/G3L SD/eMMC support
>
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
>
> RZ/G3L SoC has:
>
> Channel 0 supports SD and eMMC (including HS400/HS400ES).
> Channel 1 supports SD and eMMC (except for HS400).
> Channel 2 supports SD.
>
> The SoC supports a maximum frequency of 150 MHz. The SD0 interface does not support IOVS and PWEN in
> the SDHI register (no internal regulator), unlike SD1 and SD2. It has an internal divider for all
> modes except HS400.
> It also has a 2048-bit divider compared to 512 on others. Moreover RZ/G3L supports HS400 enhanced
> strobe mode.
>
> v1->v2:
> * Collected tag for binding patch.
> * Resending the series as there is an issue with patch threading from
> patch #14.
>
> Biju Das (17):
> dt-bindings: mmc: renesas,sdhi: Document RZ/G3L (r9a08g046) SoC
> clk: renesas: r9a08g046: Add clock and reset entries for SDHI
> pinctrl: renesas: rzg2l: Add SD channel POC support for RZ/G3L
> mmc: renesas_sdhi: Fix whitespace alignment in struct
> renesas_sdhi_of_data
> mmc: renesas_sdhi_internal_dmac: Fix whitespace alignment in struct
> initializer
> mmc: renesas_sdhi: Introduce renesas_sdhi_hw_info to abstract clock
> mask
> mmc: renesas_sdhi: Add max_divider to renesas_sdhi_hw_info
> mmc: renesas_sdhi: Add tuning_delay hw_info flag
> mmc: renesas_sdhi: Add internal_divider hw_info flag for clk rate
> adjustment
> mmc: renesas_sdhi: Add optional axis/axim reset controls
> mmc: renesas_sdhi: Add RZ/G3L SDHI support
> mmc: renesas_sdhi: Save and restore IOVS across suspend/resume
> mmc: renesas_sdhi: Add RZ/G3L HS400 support
> mmc: renesas_sdhi: Add HS400 enhanced strobe support for RZ/G3L
> arm64: dts: renesas: r9a08g046: Add SDHI nodes for RZ/G3L SoC and
> SDHI1 pincontrol on SMARC EVK
> arm64: dts: renesas: rzg3l-smarc-som: Enable SD/eMMC on SDHI0
> arm64: dts: renesas: rzg3l-smarc-som: Enable SDHI2
>
> .../devicetree/bindings/mmc/renesas,sdhi.yaml | 101 ++++++--
> arch/arm64/boot/dts/renesas/r9a08g046.dtsi | 73 +++++-
> .../boot/dts/renesas/r9a08g046l48-smarc.dts | 89 +++++++
> .../boot/dts/renesas/rzg3l-smarc-som.dtsi | 199 +++++++++++++++
> drivers/clk/renesas/r9a08g046-cpg.c | 92 +++++++
> drivers/mmc/host/renesas_sdhi.h | 25 +-
> drivers/mmc/host/renesas_sdhi_core.c | 226 +++++++++++++-----
> drivers/mmc/host/renesas_sdhi_internal_dmac.c | 71 +++++-
> drivers/mmc/host/renesas_sdhi_sys_dmac.c | 67 ++++--
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 74 ++++--
> 10 files changed, 889 insertions(+), 128 deletions(-)
>
> --
> 2.43.0