Re: [PATCH v2 2/5] KVM: x86: Expose Zhaoxin CCS (SM3 + SM4) CPUID feature

[Binbin Wu]

On 5/28/2026 11:22 AM, Ewan Hai wrote:
> Advertise the Zhaoxin CCS (Chinese Cryptography Standard) feature to
> guests via CPUID 0xC0000001 EDX bits 4 (CCS) and 5 (CCS_EN). CCS groups
> two user-mode instructions for Chinese national cryptographic
         ^
Nit: 
It's supposed to be replaced?

> primitives, documented in the Zhaoxin GMI Instruction Set Reference,
> chapter 2 ("CCS instruction group"):
> 
>   - SM3 (encoding F3 0F A6 E8, subsection 2.1) implements the SM3 hash
>     algorithm specified in GM/T 0004-2012. It supports two modes
>     selected by RAX: auto-padding stream mode (RAX=0) and pre-padded
>     block mode (RAX=-1).
> 
>   - SM4 (encoding F3 0F A7 F0, subsection 2.2) implements the SM4 block
>     cipher specified in GM/T 0002-2012, supporting ECB / CBC / CFB /
>     OFB / CTR modes via a control word in RAX, and CBC-MAC / CFB-MAC
>     when RAX bit[11] is set.
> 
> Both instructions are unprivileged (no CPL restriction) and available
> in all CPU modes, with no associated MSR control. The CCS and CCS_EN
> bits are redundant by hardware design (set or cleared together) and
> both serve purely as CPUID-level feature-presence reporting flags
> requiring no KVM emulation. Both bits are advertised because different
> software may probe either one when checking for CCS availability.
> 
> Signed-off-by: Ewan Hai <ewandevelop@xxxxxxxxx>
> ---
>  arch/x86/include/asm/cpufeatures.h | 2 ++
>  arch/x86/kvm/cpuid.c               | 2 ++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> index 20b33413189c..276e4ef90bd0 100644
> --- a/arch/x86/include/asm/cpufeatures.h
> +++ b/arch/x86/include/asm/cpufeatures.h
> @@ -140,6 +140,8 @@
>  #define X86_FEATURE_SM2_EN		( 5*32+ 1) /* "sm2_en" SM2 enabled */
>  #define X86_FEATURE_XSTORE		( 5*32+ 2) /* "rng" RNG present (xstore) */
>  #define X86_FEATURE_XSTORE_EN		( 5*32+ 3) /* "rng_en" RNG enabled */
> +#define X86_FEATURE_CCS			( 5*32+ 4) /* "ccs" SM3 + SM4 instructions */
> +#define X86_FEATURE_CCS_EN		( 5*32+ 5) /* "ccs_en" CCS enabled */
>  #define X86_FEATURE_XCRYPT		( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
>  #define X86_FEATURE_XCRYPT_EN		( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
>  #define X86_FEATURE_ACE2		( 5*32+ 8) /* "ace2" Advanced Cryptography Engine v2 */
> diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
> index 1eb4b88aaa80..8aaa3f20670e 100644
> --- a/arch/x86/kvm/cpuid.c
> +++ b/arch/x86/kvm/cpuid.c
> @@ -1276,6 +1276,8 @@ void kvm_initialize_cpu_caps(void)
>  		F(SM2_EN),
>  		F(XSTORE),
>  		F(XSTORE_EN),
> +		F(CCS),
> +		F(CCS_EN),
>  		F(XCRYPT),
>  		F(XCRYPT_EN),
>  		F(ACE2),