[PATCH v7 04/16] arm64: ras: Support RAS Common Fault Injection Model Extension
From: Ruidong Tian
Date: Tue Jun 02 2026 - 03:19:13 EST
Add inject register descripted in Common Fault Injection Model
Extension.
Signed-off-by: Ruidong Tian <tianruidong@xxxxxxxxxxxxxxxxx>
---
drivers/acpi/arm64/aest.c | 4 +++-
drivers/ras/arm64/ras-core.c | 27 +++++++++++++++++++++++++--
drivers/ras/arm64/ras.h | 10 ++++++++++
3 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/drivers/acpi/arm64/aest.c b/drivers/acpi/arm64/aest.c
index 3a813fe7047c..868013498abb 100644
--- a/drivers/acpi/arm64/aest.c
+++ b/drivers/acpi/arm64/aest.c
@@ -110,6 +110,8 @@ aest_init_node_props(struct acpi_aest_hdr *hdr, struct property_entry *props,
group_len);
props[(*p)++] = PROPERTY_ENTRY_U64("arm,error-group-base",
common->error_group_register_base);
+ props[(*p)++] = PROPERTY_ENTRY_U64("arm,fault-inject-base",
+ common->fault_inject_register_base);
len = hdr->node_interface_offset - hdr->node_specific_offset;
props[(*p)++] =
@@ -122,7 +124,7 @@ aest_init_node_props(struct acpi_aest_hdr *hdr, struct property_entry *props,
static int __init
aest_create_node_fwnode(struct acpi_aest_hdr *hdr, struct platform_device *pdev)
{
- struct property_entry props[11] = { };
+ struct property_entry props[12] = { };
int p = 0;
int ret;
diff --git a/drivers/ras/arm64/ras-core.c b/drivers/ras/arm64/ras-core.c
index 47ab78cc88d7..1dd471376449 100644
--- a/drivers/ras/arm64/ras-core.c
+++ b/drivers/ras/arm64/ras-core.c
@@ -139,6 +139,23 @@ static int ras_node_set_errgsr(struct ras_node *node, phys_addr_t base)
return 0;
}
+static int ras_node_set_inj_base(struct ras_node *node, phys_addr_t base)
+{
+ phys_addr_t inj_base = 0;
+ int ret = 0;
+
+ if (!(node->flags & AEST_XFACE_FLAG_FAULT_INJECT))
+ return 0;
+
+ ret = device_property_read_u64(node->dev, "arm,fault-inject-base",
+ &inj_base);
+ if (ret || !inj_base)
+ return -EINVAL;
+
+ node->inj = inj_base - base + node->base;
+ return 0;
+}
+
static struct ras_node *ras_init_node(struct platform_device *pdev)
{
int i, ret = 0;
@@ -204,6 +221,11 @@ static struct ras_node *ras_init_node(struct platform_device *pdev)
ret = ras_node_set_errgsr(node, mem->start);
if (ret)
return ERR_PTR(ret);
+ ret = ras_node_set_inj_base(node, mem->start);
+ if (ret)
+ return ERR_PTR(ret);
+ } else if (node->access_type == ACPI_AEST_NODE_MEMORY_MAPPED) {
+ return ERR_PTR(-EINVAL);
}
node->name = alloc_ras_node_name(node);
@@ -221,8 +243,9 @@ static struct ras_node *ras_init_node(struct platform_device *pdev)
if (ret)
return ERR_PTR(ret);
}
- ras_node_dbg(node, "base: %llx, access_type: %s\n",
- node->addr, node->access_type ? "MMIO" : "Register");
+ ras_node_dbg(node, "base: %llx, access_type: %s, %s inject\n",
+ node->addr, node->access_type ? "MMIO" : "Register",
+ node->flags & AEST_XFACE_FLAG_FAULT_INJECT ? "with" : "without");
return node;
}
diff --git a/drivers/ras/arm64/ras.h b/drivers/ras/arm64/ras.h
index 94ffeb83b251..da03593e5f7f 100644
--- a/drivers/ras/arm64/ras.h
+++ b/drivers/ras/arm64/ras.h
@@ -54,6 +54,9 @@
#define ERXMISC1 0x28
#define ERXMISC2 0x30
#define ERXMISC3 0x38
+#define ERXPFGF 0x800
+#define ERXPFGCTL 0x808
+#define ERXPFGCDN 0x810
struct ras_access {
u64 (*read)(void __iomem *base, u32 offset);
@@ -85,6 +88,7 @@ struct ras_node {
void __iomem *base;
void __iomem *errgsr;
+ void __iomem *inj;
phys_addr_t addr;
u8 *specific_data;
@@ -147,6 +151,9 @@ static inline u64 ras_sysreg_read(void __iomem *base __always_unused, u32 offset
CASE_READ(res, ERXMISC1)
CASE_READ(res, ERXMISC2)
CASE_READ(res, ERXMISC3)
+ CASE_READ(res, ERXPFGF)
+ CASE_READ(res, ERXPFGCTL)
+ CASE_READ(res, ERXPFGCDN)
default:
res = 0;
}
@@ -164,6 +171,9 @@ static inline void ras_sysreg_write(void __iomem *base __always_unused, u32 offs
CASE_WRITE(val, ERXMISC1)
CASE_WRITE(val, ERXMISC2)
CASE_WRITE(val, ERXMISC3)
+ CASE_WRITE(val, ERXPFGF)
+ CASE_WRITE(val, ERXPFGCTL)
+ CASE_WRITE(val, ERXPFGCDN)
default:
return;
}
--
2.51.2.612.gdc70283dfc