Re: [PATCH 3/3] clk: qcom: add MSM8x60 MMCC driver

[Herman van Hazendonk]

Hi,

Confirmed -- thanks for catching this. mmcc_msm8660_resets[] jumps
straight from FABRIC_AHB_RESET (29) to GFX3D_AHB_RESET (32). Array
indices 30 (GFX2D0_AHB_RESET) and 31 (GFX2D1_AHB_RESET) were
implicitly zero-initialised, so when gfx2d0_gdsc / gfx2d1_gdsc
power-cycle the GDSC the qcom_reset_set_assert() path does a RMW
on { .reg = 0, .bit = 0 } -- toggling bit 0 of register 0x0000
(MMSS PLL0 mode register) on every transition. Genuine silent
clock-controller corruption, not just a missing reset toggle.

v2 will add:

    [GFX2D0_AHB_RESET] = { 0x020c, 12 },
    [GFX2D1_AHB_RESET] = { 0x020c, 11 },

between the FABRIC_AHB_RESET and GFX3D_AHB_RESET entries. Bit
positions match the sibling mmcc-msm8960.c driver -- same hardware
IP, same MMSS_AHB_RESET register layout.

Fix is in my local tree and on-device validated; will land in v2
alongside the unhalt_fabric_ports() -EPROBE_DEFER fix and the
cover-letter dependency on the gdsc framework series:

    https://lore.kernel.org/linux-clk/20260602050840.435933-1-github.com@xxxxxxxxxx/

On the "MSSS vs MMSS" naming nit: agreed it should be MMSS_, but
that one I'll leave for a separate cleanup so v2 doesn't churn DT
ABI alongside the functional fixes.

Thanks,
Herman