[PATCH v3 12/12] arm64: dts: qcom: agatti: Add DSI1 PHY and sleep clocks to DISPCC node
From: Imran Shaik
Date: Mon Jun 01 2026 - 14:38:59 EST
Update the DISPCC node on QCM2290 (Agatti) to align with the latest DT
bindings changes, which adds support for the DSI1 PHY and sleep clocks.
Signed-off-by: Imran Shaik <imran.shaik@xxxxxxxxxxxxxxxx>
---
arch/arm64/boot/dts/qcom/agatti.dtsi | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/agatti.dtsi b/arch/arm64/boot/dts/qcom/agatti.dtsi
index 8a7337239b1ebe2c40d64ed670752a680085b871..d8b07db81ace41f6fe2c7139ef283bea0d0c3da9 100644
--- a/arch/arm64/boot/dts/qcom/agatti.dtsi
+++ b/arch/arm64/boot/dts/qcom/agatti.dtsi
@@ -2137,13 +2137,19 @@ dispcc: clock-controller@5f00000 {
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>,
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
- <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
+ <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <0>,
+ <0>,
+ <&sleep_clk>;
clock-names = "bi_tcxo",
"bi_tcxo_ao",
"gcc_disp_gpll0_clk_src",
"gcc_disp_gpll0_div_clk_src",
"dsi0_phy_pll_out_byteclk",
- "dsi0_phy_pll_out_dsiclk";
+ "dsi0_phy_pll_out_dsiclk",
+ "dsi1_phy_pll_out_byteclk",
+ "dsi1_phy_pll_out_dsiclk",
+ "sleep_clk";
#power-domain-cells = <1>;
#clock-cells = <1>;
#reset-cells = <1>;
--
2.34.1