Re: [PATCH v11 06/22] gpu: nova-core: Blackwell: use correct sysmem flush registers

From: Alexandre Courbot

Date: Mon Jun 01 2026 - 09:18:12 EST


On Mon Jun 1, 2026 at 4:33 PM JST, Eliot Courtney wrote:
> On Sat May 30, 2026 at 12:09 PM JST, John Hubbard wrote:
>> +
>> + // Blackwell GB10x sysmem flush registers (HSHUB0).
>> + //
>> + // GB10x GPUs use two pairs of HSHUB registers for sysmembar: a primary pair and an EG
>> + // (egress) pair. Both must be programmed to the same address. Hardware ignores bits 7:0
>> + // of each LO register. HSHUB0 base is 0x00891000.
>> +
>> + pub(crate) NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x00891e50 {
>> + 31:0 adr => u32;
>> + }
>> +
>> + pub(crate) NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00891e54 {
>> + 19:0 adr;
>> + }
>> +
>> + pub(crate) NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008916c0 {
>> + 31:0 adr => u32;
>> + }
>> +
>> + pub(crate) NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008916c4 {
>> + 19:0 adr;
>> + }
>> +
>> + // Blackwell GB20x sysmem flush registers (FBHUB0).
>> + //
>> + // Unlike the older NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which encode the address with an
>> + // 8-bit right-shift, these registers take the raw address split into lower/upper 32-bit halves.
>> + // The hardware ignores bits 7:0 of the LO register.
>> +
>> + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008a1d58 {
>> + 31:0 adr => u32;
>> + }
>> +
>> + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008a1d5c {
>> + 19:0 adr;
>> + }
>> }
>
> May be nice to move these to the place (HAL) they are used if they
> aren't used anywhere else (and reduce visibility).

Indeed, we have a thread on Zulip [1] suggesting to move register
definitions into subdevice-level `regs.rs` modules. I guess we could
proactively start doing this with these new registers; on the other
hand, I'm also fine with keeping the current pattern and doing the move
later if John prefers to keep things the current way.

[1] https://rust-for-linux.zulipchat.com/#narrow/channel/509436-Nova/topic/.5BRFC.5D.20Moving.20register.20definitions.20into.20the.20module.20using.20them/with/599138666