Re: [PATCH] clk: samsung: exynos990: Fix PERIC0/1 USI clock types

[Krzysztof Kozlowski]

On Thu, 28 May 2026 15:09:01 -0500, Denzeel Oliva wrote:
> Use nMUX() for USI and UART user muxes to allow reparenting between
> OSC and CMU IP output when changing rates, and use DIV_F() with
> CLK_SET_RATE_PARENT on their dividers and gates so rate requests
> propagate upward.
> 
> Consolidate identical USI parent arrays into shared
> mout_peric0_nonbususer_p and mout_peric1_nonbususer_p.
> 
> [...]

Applied, thanks!

[1/1] clk: samsung: exynos990: Fix PERIC0/1 USI clock types
      https://git.kernel.org/krzk/linux/c/e11560b050ce867bd7d3ccea138231db54e2250a

Best regards,
-- 
Krzysztof Kozlowski <krzk@xxxxxxxxxx>