Re: (subset) [PATCH v3 0/2] PCI: tegra194: ASPM L1 entrance latency from device tree

[Thierry Reding]

From: Thierry Reding <treding@xxxxxxxxxx>


On Fri, 15 May 2026 12:37:51 +0530, Manikanta Maddireddy wrote:
> This series programs Synopsys DesignWare ASPM L1 entrance latency on NVIDIA
> Tegra194/234 PCIe controllers from an optional device tree property and
> corrects the default nanosecond cells so the PORT_AFR field advertises the
> intended latency buckets.
> 
> Background
> ----------
> The controller exposes L1 entrance latency in PCI Express PORT_AFR (DW DBI),
> bits 27:29.  Software must select a 3-bit code for the maximum L1 entry delay
> the platform can tolerate.  Patch 1 reads aspm-l1-entry-delay-ns (nanoseconds),
> converts to whole microseconds with ceiling division (DIV_ROUND_UP), and
> programs min(order_base_2(us), 7) into PORT_AFR during ASPM init.  If the
> property is absent, the driver keeps the existing default (code 7).
> 
> [...]

Applied, thanks!

[2/2] arm64: tegra: fix aspm-l1-entry-delay-ns L1 latency cells
      commit: 56c5f525817ea99ce34110700b3a0ab71add0b8c

Best regards,
-- 
Thierry Reding <treding@xxxxxxxxxx>