Re: [PATCH v4 16/39] drm/msm/dp: use stream_id to change offsets in dp_catalog
From: Yongxing Mou
Date: Mon May 25 2026 - 08:13:48 EST
On 5/25/2026 4:21 PM, Dmitry Baryshkov wrote:
On Mon, May 25, 2026 at 04:06:08PM +0800, Yongxing Mou wrote:Hmm. So should I just delete this comments and sort them in ascending address order? Regarding REG_DP1_ and MMSS_DP1_, this is a historical naming convention inherited from the existing code.
On 4/12/2026 2:12 AM, Dmitry Baryshkov wrote:
On Fri, Apr 10, 2026 at 05:33:51PM +0800, Yongxing Mou wrote:Got it, thanks.
From: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
Use the dp_panel's stream_id to adjust the offsets for stream 1 which will
be used for MST in the dp_catalog.
Please start by describing the problem.
Here also from DPTX_*, what about this? /* DP_TX MST registers */Stream 1 share the same link clk with
stream 0 with different reg offset. Also add additional register defines
for stream 1.
Streams 2 and 3 are not covered here, as they use separate link clocks and
require separate handling.
Signed-off-by: Abhinav Kumar <quic_abhinavk@xxxxxxxxxxx>
Signed-off-by: Yongxing Mou <yongxing.mou@xxxxxxxxxxxxxxxx>
---
drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 ++++++++++---
drivers/gpu/drm/msm/dp/dp_panel.c | 72 +++++++++++++++++++++++++++------------
drivers/gpu/drm/msm/dp/dp_reg.h | 11 ++++++
3 files changed, 81 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h
index 3689642b7fc0..295c1161e6b7 100644
--- a/drivers/gpu/drm/msm/dp/dp_reg.h
+++ b/drivers/gpu/drm/msm/dp/dp_reg.h
@@ -332,6 +332,17 @@
#define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001)
#define DP_TPG_VIDEO_CONFIG_RGB (0x00000004)
+/* DP MST registers */
Which register spaces are they from?
Why? don't separate them from the registers from the same space. Also,
please, name them uniformly. Why some of those are REG_DP1 and others
are MMSS_DP1?
+#define REG_DP1_CONFIGURATION_CTRL (0x00000400)
+#define REG_DP1_SOFTWARE_MVID (0x00000414)
+#define REG_DP1_SOFTWARE_NVID (0x00000418)
+#define REG_DP1_TOTAL_HOR_VER (0x0000041C)
+#define REG_DP1_MISC1_MISC0 (0x0000042C)
+#define MMSS_DP1_GENERIC0_0 (0x00000490)
+#define MMSS_DP1_SDP_CFG (0x000004E0)
+#define MMSS_DP1_SDP_CFG2 (0x000004E4)
+#define MMSS_DP1_SDP_CFG3 (0x000004E8)
+
#define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088)
#define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C)