Re: [PATCH 3/5] irqchip/qcom-pdc: Configure PDC to pass through mode

[Stephan Gerhold]

On Fri, Mar 13, 2026 at 12:49:22PM +0100, Konrad Dybcio wrote:
> On 3/13/26 7:40 AM, Maulik Shah (mkshah) wrote:
> > On 3/13/2026 7:52 AM, Dmitry Baryshkov wrote:
> >> On Thu, Mar 12, 2026 at 09:26:37PM +0530, Maulik Shah wrote:
> 
> [...]
> 
> >>> All the SoCs so far default uses pass through mode with the exception of
> >>
> >> Is it something that must be configured by the bootloaders?
> > 
> > yes, currently changing the the mode can be done from secure world either at boot
> > or after boot via scm write.
> 
> ..which won't work on almost any X1E devices, except CRD and IOT..
> 

FWIW: The "actively-maintained" X1E Windows laptops (e.g. T14s, Dell
XPS) have received support for the new SCM call through BIOS updates
sometime last year when the BSP was upgraded. There will, however,
always be devices that are stuck at their original launch time BIOS,
unfortunately. Those will not be able to use the SCM call.

> >>> x1e. x1e PDC may be set to secondary controller mode for builds on CRD
> >>> boards whereas it may be set to pass through mode for IoT-EVK.
> >>>
> >>> There is no way to read which current mode it is set to and make PDC work
> >>> in respective mode as the read access is not opened up for non secure
> >>> world. There is though write access opened up via SCM write API to set the
> >>> mode.
> >>
> >> What are going to loose? The ability to latch the wakeup sources on the
> >> CRD?
> > 
> > CXPC (SoC level low power mode) would be lost if the device can not wake up from GPIO wakeup sources.
> 
> To the best of my understanding, that's only because your approach chooses
> to ignore supporting the secondary controller mode and force-reconfigure,
> since GPIO wakeup functionality is otherwise available regardless of the
> mode.
> 
> >>> Configure PDC mode to pass through mode for all x1e based boards via SCM
> >>> write.
> >>
> >> Would it make sense to always use the secondary mode instead?
> > 
> > No, it would not make sense to support the secondary mode in Linux.
> 
> Why?
> 
> [...]
> 
> >>> +		 *	- Inform TLMM to monitor GPIO IRQs (same as MPM)
> >>> +		 *	- Prevent SoC low power mode (CxPC) as PDC is not
> >>> +		 *	  monitoring GPIO IRQs which may be needed to wake
> >>> +		 *	  the SoC from low power mode.
> >>
> >> This doesn't quite match the description of "latches the GPIO IRQs".
> > 
> > It does, PDC would continue to still latch the GPIO IRQs (as the mode change failed)
> > but PDC won't forward them to parent GIC as they are masked at PDC with __pdc_mask_intr().
> 
> Can you not refrain from masking them then, and clear them upon reception,
> with a write to IRQ_i_CFG[IRQ_STATUS]?
> 
> The HPG states that this mechanism is only engaged for GPIO IRQs and that
> the forwarded interrupt will be of LEVEL_HIGH type (which is what TLMM
> accepts anyway)
> 
> FWIW, some related work:
> c7984dc0a2b9 ("pinctrl: qcom: Add test case for TLMM interrupt handling")
> 

All these changes actually exist already. I created 3 different patch
sets for the PDC on X1E at some point:

 1. SCM call only with "no deep suspend wakeup" for older firmwares
 2. Support for secondary/auxiliary interrupt controller with fallback
    to SCM call if supported
 3. Unconditional use of secondary/auxiliary interrupt controller for
    all firmware versions

If I remember correctly, the preferred option in discussions with
Bjorn/Johan back then was to go with option (3). We wanted to support
all X1E laptops and the additional effort of supporting two different
interrupt handling approaches on a single platform did not seem worth
it. In addition, there were reported crashes when resuming from suspend
when using the SCM call approach (but not using the secondary interrupt
controller feature). The crashdump was pointing to unrelated SMMU
problems, but perhaps that was just coincidental. It could be perhaps
related to the recently fixed USB clock issue [1]. Not sure, but if we
end up using the SCM call we should test that to be sure.

I was not able to post these patches upstream back then because of
ongoing discussions about the errata handling etc, but I think Maulik
should have a copy of them. I was close to submitting option (3), it
passes all tlmm-test cases except one related to latching of interrupts
while disabled. The intended behavior of that is not well-defined in the
Linux API.

I pushed the latest draft to a public repo sometime last year. That repo
is not available anymore, but I have now restored the branch here:
https://github.com/stephan-gh/linux/commits/wip/x1e80100-6.15-pdc/

You can find details about the open test failure in this commit:
https://github.com/stephan-gh/linux/commit/59ca2a7335ede83e4a7cf02704dd7c469c725c14

Thanks,
Stephan

[1]: https://lore.kernel.org/linux-arm-msm/36bbe3c6-e83d-48be-8a9c-9cbc5b26e064@xxxxxxxxxxxxxxxx/