Re: [PATCH v3 2/7] platform/x86/amd/hsmp: Add UAPI structures for Family 1Ah Model 50h-5Fh metrics table

[Ilpo Järvinen]

On Sun, 17 May 2026, Muralidhara M K wrote:

> Define the UAPI structures hsmp_metric_table_zen6_iod,
> hsmp_metric_table_zen6_ccd and the top-level hsmp_metric_table_zen6
> to describe the per-IOD and per-CCD metrics layout for AMD Family 1Ah
> Model 50h-5Fh processors (HSMP protocol version 7).  These structures
> allow userspace tools to interpret the raw metric table binary exposed
> through the HSMP character device.
> 
> Driver enablement for protocol version 7 is added in a follow-up patch.
> 
> Reviewed-by: Suma Hegde <suma.hegde@xxxxxxx>
> Co-developed-by: Muthusamy Ramalingam <muthusamy.ramalingam@xxxxxxx>
> Signed-off-by: Muthusamy Ramalingam <muthusamy.ramalingam@xxxxxxx>
> Signed-off-by: Muralidhara M K <muralidhara.mk@xxxxxxx>
> ---
> Changes:
> v1->v2: Split the change
> v2->v3: Move proto version check to seperate patch
> 
>  arch/x86/include/uapi/asm/amd_hsmp.h | 88 ++++++++++++++++++++++++++++
>  1 file changed, 88 insertions(+)
> 
> diff --git a/arch/x86/include/uapi/asm/amd_hsmp.h b/arch/x86/include/uapi/asm/amd_hsmp.h
> index 603d62f8d4da..da3e3bbfa33e 100644
> --- a/arch/x86/include/uapi/asm/amd_hsmp.h
> +++ b/arch/x86/include/uapi/asm/amd_hsmp.h
> @@ -575,6 +575,94 @@ struct hsmp_metric_table {
>  	__u32 gfxclk_frequency[8];
>  };
>  
> +#define F1A_M50_M5F_MAX_CORES_PER_CCD_32	32
> +#define F1A_M50_M5F_MAX_FREQ_TABLE_SIZE		4
> +#define F1A_M50_M5F_MAX_XGMI			8
> +#define F1A_M50_M5F_MAX_PCIE			8
> +#define F1A_M50_M5F_MAX_CCD			8

Should have a prefix.

> +
> +/* Metrics table (supported only with proto version 7) */
> +struct hsmp_metric_table_zen6_iod {
> +	__u32 num_active_ccds;
> +	__u32 accumulation_counter;
> +
> +	/* TEMPERATURE */
> +	__u64 max_socket_temperature_acc;
> +
> +	/* POWER */
> +	__u32 socket_power_limit;
> +	__u32 max_socket_power_limit;
> +	__u64 socket_power_acc;
> +	__u64 core_power_acc;
> +	__u64 uncore_power_acc;
> +
> +	/* ENERGY */
> +	__u64 timestamp;
> +	__u64 socket_energy_acc;
> +	__u64 core_energy_acc;
> +	__u64 uncore_energy_acc;
> +
> +	/* FREQUENCY */
> +	__u64 fclk_frequency_acc;
> +	__u64 uclk_frequency_acc;
> +	__u64 ddr_rate_acc;
> +	__u64 lclk_frequency_acc[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE];
> +
> +	/* FREQUENCY RANGE */
> +	__u32 fclk_frequency_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE];
> +	__u32 uclk_frequency_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE];
> +	__u32 ddr_rate_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE];
> +	__u32 max_df_pstate_range;
> +	__u32 min_df_pstate_range;
> +	__u32 lclk_frequency_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE];
> +	__u32 max_lclk_dpm_range;
> +	__u32 min_lclk_dpm_range;
> +
> +	/* XGMI */
> +	__u64 xgmi_bit_rate[F1A_M50_M5F_MAX_XGMI];
> +	__u64 xgmi_read_bandwidth[F1A_M50_M5F_MAX_XGMI];
> +	__u64 xgmi_write_bandwidth[F1A_M50_M5F_MAX_XGMI];
> +
> +	/* ACTIVITY */
> +	__u64 socket_c0_residency_acc;
> +	__u64 socket_df_cstate_residency_acc;
> +	__u64 dram_read_bandwidth_acc;
> +	__u64 dram_write_bandwidth_acc;
> +	__u32 max_dram_bandwidth;
> +	__u64 pcie_bandwidth_acc[F1A_M50_M5F_MAX_PCIE];
> +
> +	/* THROTTLERS */
> +	__u32 prochot_residency_acc;
> +	__u32 ppt_residency_acc;
> +	__u32 thm_residency_acc;
> +	__u32 vrhot_residency_acc;
> +	__u32 cpu_tdc_residency_acc;
> +	__u32 soc_tdc_residency_acc;
> +	__u32 io_mem_tdc_residency_acc;
> +	__u32 fit_residency_acc;
> +};
> +
> +struct hsmp_metric_table_zen6_ccd {
> +	__u32 core_apicid_of_thread0[F1A_M50_M5F_MAX_CORES_PER_CCD_32];
> +	__u64 core_c0[F1A_M50_M5F_MAX_CORES_PER_CCD_32];
> +	__u64 core_cc1[F1A_M50_M5F_MAX_CORES_PER_CCD_32];
> +	__u64 core_cc6[F1A_M50_M5F_MAX_CORES_PER_CCD_32];
> +	__u64 core_frequency[F1A_M50_M5F_MAX_CORES_PER_CCD_32];
> +	__u64 core_frequency_effective[F1A_M50_M5F_MAX_CORES_PER_CCD_32];
> +	__u64 core_power[F1A_M50_M5F_MAX_CORES_PER_CCD_32];
> +};
> +
> +/*
> + * Metrics table for Family 0x1A, Models 0x50 to 0x5F, table version 0x00700000
> + *
> + * Future processors within the same family and model may support a
> + * variable number of CCDs and cores

How is the correct number of CCDs then known?

If it's through num_active_ccds, I question if hsmp_metric_table_zen6 
struct hierarchy is correct as then something under iod seems to 
determine how to interpret the ccd[] array.

> + */
> +struct hsmp_metric_table_zen6 {
> +	struct hsmp_metric_table_zen6_iod iod;
> +	struct hsmp_metric_table_zen6_ccd ccd[F1A_M50_M5F_MAX_CCD];
> +};
> +
>  /* Reset to default packing */
>  #pragma pack()
>  
> 

-- 
 i.